Fairchild Semiconductor 74ACQ241SCX, 74ACQ241SC, 74ACQ241PC, 74ACQ241MSA, 74ACQ241CW Datasheet

January 1990
Revised September 1998

74ACQ241 Octal Buffer/Line Driver with 3-STATE Outputs

© 1998 Fairchild Semiconductor Corporation DS010642.prf www.fairchildsemi.com

74ACQ241
Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The ACQ241 is an oct al buffer and line drive r designed to
be employed as a m em ory add re ss dr i ver, clock driver a nd
bus oriented transmitter or receiver which provides
improved PC board density. The ACQ utilizes Fairchild
FACT Quiet Series technology to guarantee quiet output
switching and improved dynamic threshold performance.
FACT Quiet Series features GTO output control and
undershoot corr ector in addition to a split ground bus for
superior performance.

Features

■ ICC and IOZ reduced by 50%

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Guaranteed pin-to-pin skew AC performance

■ Improved latch-up immunity

■ 3-STATE outputs drive bus lines or buffer memory

address registers

■ Outputs source/sink 24 mA

■ Faster prop delays than the standard AC

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering co de.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Assignme nt for DIP and SOIC

Pin Descriptions

Truth Tables

H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance

FACT, FACT Quiet Series, a nd GTO are trademarks of F airchild Semicond uc t or Corporation .

Order Number Package Number Package Description

74ACQ241SC M20B 20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body
74ACQ241PC N20A 20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300” Wide

Pin Names Description

OE

1

, OE

2

3-STATE Output Enable Inputs

I

0–I7

Inputs

O

0–O7

Outputs

Inputs Outputs

OE

1

I

n

(Pins 12, 14, 16, 18)

LL L
LH H

HX Z

Inputs Outputs

OE

2

I

n

(Pins 3, 5, 7, 9)

HL L
HH H
HX Z

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74ACQ241

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with­out exception, to ensure that the system design is reliable over its po wer
supply, temperature, and output /input lo ading variable s. Fairch ild do es not
recommend operation of FACT circuits out s ide databook specifications.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source

or Sink Current (I

O

) ± 50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ± 50 mA

Storage Temperature (T

STG

) −65°C to +150°C

DC Latch-Up Source or

Sink Current ±300 mA

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

) 2.0V to 6.0V

Input Voltage (V

I

) 0V to V

CC

Output Voltage (VO) 0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t 125 mV/ns

V

IN

from 30% to 70% of V

CC

VCC @ 3.0V, 4.5V, 5.5V

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74ACQ241

DC Electrical Characteristics

Note 2: All outputs loaded; thresholds on input assoc iated with outpu t un der test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I

IN

and ICC @ 3.0V are guar ant eed to be less tha n or equal to the respe ctiv e limit @ 5.5V VCC.

Note 5: DIP packa ge.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. n−1 Inputs s w it c hing 0V to 5V . Input- under-test switch ing: 5V to threshol d (V

ILD

), 0V to threshold (V

IHD

),

f = 1 MHz.

Symbol Parameter V

CC

TA = +25°CT

A

= −40°C to +85°C Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum High Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum Low Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum High Level 3.0 2.99 2.9 2.9 I

OUT

= −50 µA

Output Voltage 4.5 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4
VIN = VIL or V

IH

3.0 2.56 2.46

V

IOH = −12 mA

4.5 3.86 3.76 IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

V

OL

Maximum Low Level 3.0 0.002 0.1 0.1 I

OUT

= 50 µA

Output Voltage 4.5 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1
VIN = VIL or V

IH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

I

IN

(Note 4)

Maximum Input Leakage Current

5.5 ± 0.1 ± 1.0 µA

VI = VCC, GND

I

OLD

Minimum Dynamic
Output Current

5.5 75 mA V

OLD

= 1.65V Max

I

OHD

(Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

(Note 4)

Maximum Quiescent
Supply Current

5.5 4.0 40.0 µA

VIN = VCC or GND

I

OZ

Maximum 3-STATE 5.5 ±0.25 ±2.5 µAVI (OE) = VIL, V

IH

Leakage Current VI = VCC, GND

VO = VCC, GND

V

OLP

Quiet Output 5.0 1.1 1.5 V Figures 1, 2
Maximum Dynamic V

OL

(Note 5)(Note 6)

V

OLV

Quiet Output 5.0 −0.6 −1.2 V Figures 1, 2
Minimum Dynamic V

OL

(Note 5)(Note 6)

V

IHD

Minimum High Level 5.0 3.1 3.5 V (Note 5)(Note 7)
Dynamic Input Voltage

V

ILD

Maximum Low Level 5.0 1.9 1.5 V (Note 5)(Note 7)
Dynamic Input Voltage