Fairchild Semiconductor 74AC821SPC, 74AC821SCX, 74AC821SC, 74AC821CW Datasheet

© 2000 Fairchild Semiconductor Corporation DS010139 www.fairchildsemi.com
November 1988 Revised August 2000
74AC821 • 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs
74AC821 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE outputs arranged in a broadside pinout.
Features
3-STATE outputs for bus interfacing
Noninverting outputs
Outputs source/sink 24 mA
TTL compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT821MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0–D9
Data Inputs
O
0–O9
Data Outputs
OE
Output Enable Input
CP Clock Input
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74AC821 74ACT821
Functional Description
The AC/ACT821 co nsists of ten D-type edge -tr i gge re d f lip ­flops. The buffered Clock (CP) and buffered Output Enable (OE
) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition.
With OE
LOW the contents of the fl ip -flop s a re ava il able at
the outputs. When OE
is HIGH the outputs go to the high
impedance state. Operation of the OE
input does not affect
the state of the flip-flops.
Function Table
H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance
= LOW-to-HIGH Clo c k Transi ti on
Logic Diagram
Please note that this di agram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Internal Outputs
Function
OE
CP D Q O
H
L L Z High Z
H
H H Z High Z
L
LL LLoad
L
HH HLoad
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74AC821 74ACT821
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute max imum ratings are those values beyond which damage
to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specif ic at ions.
DC Electrical Characteristics for AC
Note 2: All outputs loaded; thres holds on input associate d w it h output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.
Supply Voltage (VCC) 0.5V to + 7.0V DC Input Diode Current (I
IK
)
V
I
= 0.5V 20 mA
V
I
= VCC + 0.5V + 20 mA
DC Input Voltage (V
I
) 0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= 0.5V 20 mA
V
O
= VCC + 0.5V + 20 mA
DC Output Voltage (V
O
) 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ± 50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ± 50 mA
Storage Temperature (T
STG
) 65°C to + 150°C
Junction Temperature (T
J
)
PDIP 140
°C
Supply Voltage (V
CC
) AC 2.0V to 6.0V ACT 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) 40°C to + 85°C Minimum Input Edge Rate (
V/t)
AC Devices V
IN
from 30% to 70% of V
CC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (
V/t)
ACT Devices V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CTA = 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= 50 µA
5.5 5.49 5.4 5.4 VIN = VIL or V
IH
3.0 2.56 2.46 IOH = 12 mA
4.5 3.86 3.76 V I
OH
= 24 mA
5.5 4.86 4.76 I
OH
= 24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1 VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µAVI = VCC, GND I
OZ
Maximum 3-STATE Current VI (OE) = VIL, V
IH
5.5 ±0.5 ±5.0 µAVI = VCC, GND VO = VCC, GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 −75 mA V
OHD
= 3.85V Min
ICC (Note 4) Maximum Quiescent Supply Current 5.5 8.0 80.0 µAVIN = VCC or GND
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