Fairchild Semiconductor 74AC648SPC, 74AC648SCX, 74AC648SC, 74AC648CW Datasheet

© 2000 Fairchild Semiconductor Corporation DS010133 www.fairchildsemi.com

November 1988
Revised August 2000

74AC648 Octal Transceiver/Register with 3-STATE Outputs

74AC648
Octal Transceiver/Register with 3-STATE Outputs

General Description

The AC648 consists of register ed bus transceiver circ uits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of da ta directly from the input bus
or from the interna l storage registers . Data on the A or B
bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functio ns
available are illustra ted i n Fi gur e 1 , Fi g ur e 2, Figure 3, and
Figure 4.

Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data transfers

■ 3-STATE outputs

■ 300 mil slim dual-in-line package

■ Outputs source/sink 24 mA

■ Inverted data to output

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC648SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC648SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

A

0–A7

Data Register A Inputs,
Data Register A 3-STATE Outputs

B

0

– B

7

Data Register B Inputs,

Data Register B 3-STATE Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Transmit/Receive Inp uts
DIR, G

Output Enable Inputs

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74AC648

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Irreleva nt



= LOW-to-HIGH Transition

Note 1: The data output functions may be enabled or disabled by various signals at the G

and DIR input s . D ata input func tions are always enabled; i.e., dat a

at the bus pins will be s to red on every LOW-to-HIG H tra ns it ion of the clock inputs.

Real Time Transfer

A-Bus to B-Bus

FIGURE 1.

Real Time Transfer

B-Bus to A-Bus

FIGURE 2.

Storage from

Bus to Register

FIGURE 3.

Transfer from

Register to Bus

FIGURE 4.

Inputs Data I/O (Note 1) Function

G

DIR CPAB CPBA SAB SBA A0–A7B0–B

7

H X H or L H or L X X Isolation
HX



X X X Input Input Clock An Data into A Register

HX X



X X Clock Bn Data into B Register

LHXXLX A

n

to Bn—Real Time (Transparent Mode)

LH



X L X Input Output Clock An Data into A Register

L H H or L X H X A Register to B

n

(Stored Mode)

LH



X H X Clock An Data into A Register and Output to B

n

LLXXXL Bn to An —Real Time (Transparent Mode)
LLX



X L Output Input Clock Bn Data into B Register

L L X H or L X H B Register to A

n

(Stored Mode)

LLX



X H Clock Bn Data into B Register and Output to A

n

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74AC648

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.