Fairchild Semiconductor 74AC646SC, 74AC646CW, 74AC646SPC, 74AC646SCX Datasheet
November 1988
Revised December 1998
74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs
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74AC646 • 74ACT646
Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC/ACT646 consist of registe red bus transceiver circuits, with outputs, D-type flip-flops and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental data handling
functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4.
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data transfers
■ 3-STATE outputs
■ 300 mil dual-in-line package
■ Outputs source/sink 24 mA
■ ACT646 has TTL compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Assignment
for DIP and SOIC
Pin Descriptions
FACT is a tra demark of Fairchild Semico nductor Corporation.
Order Number Package Number Package Description
74AC646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
74ACT646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Pin Names Description
A
0–A7
Data Register A Inputs
Data Register A Outputs
B
0–B7
Data Register B Inputs
Data Register B Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Transmit/Receive Inputs
G
Output Enable Input
DIR Direction Control Input
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74AC646 • 74ACT646
Function Table
H = HIGH Voltage Level
L = LOW V oltage Leve l
X = Immaterial
= LOW-to-HIGH Transition
Note 1: The data output fu nc t ions may be enabled or disabled by various signals at the G
and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of t he appropriate clock inputs.
Real Time Transfer
A-Bus to B-Bus
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
FIGURE 2.
Storage from
Bus to Register
FIGURE 3.
Transfer from
Register to Bus
FIGURE 4.
Inputs Data I/O (Note 1) Function
G
DIR CPAB CPBA SAB SBA A0–A7B0–B
7
H X H or L H or LXX Isolation
HX
X X X Input Input Clock An Data into A Register
HXX
X X Clock Bn Data into B Register
LHXXLX A
n
to Bn—Real Time (Transparent Mode)
LH
X L X Input Output Clock An Data into A Register
L H H or L X H X A Register to B
n
(Stored Mode)
LH
X H X Clock An Data into A Register and Output to B
n
LLXXXL Bn to An —Real Time (Transparent Mode)
LLX
X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to A
n
(Stored Mode)
LLX
X H Clock Bn Data into B Register and Output to A
n
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74AC646 • 74ACT646
Logic Diagram
Please note that this d iagram is provided only for the understanding of logic operations and should no t b e us ed to estimate propagation delays.
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