Fairchild Semiconductor 74AC573SJX, 74AC573SJ, 74AC573SCX, 74AC573SC, 74AC573PC Datasheet
...
© 1999 Fairchild Semiconductor Corporation DS009973 www.fairchildsemi.com
November 1988
Revised October 1999
74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs
74AC573 • 74ACT573
Octal Latch with 3-STATE Outputs
General Description
The 74AC573 and 74ACT 573 are high-speed oct al l atch es
with buffered common Latch Enable (LE) and buffered
common Output Enable (OE
) inputs.
The 74AC573 and 74ACT 573 are functionally id entical to
the 74AC373 and 74ACT373 but with i nputs and outputs
on opposite sides.
Features
■ ICC and IOZ reduced by 50%
■ Inputs and outputs on op posite sides of package allow -
ing easy interface with microprocessors
■ Useful as input or output port for microprocessors
■ Functionally identical to 74AC373 and 74ACT373
■ 3-STATE outputs for bus interfacing
■ Outputs source/sink 24 mA
■ 74ACT573 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trade m ark of F airchild Semicondu ctor Corporation.
Order Number Package Number Package Description
74AC573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74AC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74ACT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
3-STATE Output Enable Input
O
0–O7
3-STATE Latch Outputs
www.fairchildsemi.com 2
74AC573 • 74ACT573
Functional Description
The 74AC573 and 74ACT 573 co ntain e ight D -type latches
with 3-STATE output buffers. Whe n the Latch Enab le (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are t ransparent, i.e., a latch output will change state each time its D-typ e input changes.
When LE is LOW the latches store the information that was
present on the D-type inputs a setup time pre ceding the
HIGH-to-LOW trans ition of LE. The 3-STATE buffers are
controlled by the Output Ena ble (OE
) input. When OE is
LOW, the buffers are enabled. When OE
is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O
0
= Previous O0 before HIGH-to-LOW t ransition of Latch Ena ble
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Inputs Outputs
OE
LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
3 www.fairchildsemi.com
74AC573 • 74ACT573
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut load ing vari ables. Fairchild does n ot
recommend operat ion of FACT circuits outside da t abook specifications.
DC Electrical Characteristics for AC
Note 2: All outputs loaded; thresholds on input associated with out put under test.
Note 3: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V VCC.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
(PDIP) 140°C
Supply Voltage (V
CC
)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (VO)0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1
V
V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9
V
V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
V
I
OUT
= −50 µA
Output Voltage 4.5 4.49 4.4 4.4
5.5 5.49 5.4 5.4
V
VIN = VIL or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 IOH = −24 mA
5.5 4.86 4.76 IOH = −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
VI
OUT
= 50 µAOutput Voltage 4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
V
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN (Note 3) Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAVI = VCC, GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 4) 5.5 −75 mA V
OHD
= 3.85V Min
ICC Maximum Quiescent
5.5 4.0 40.0 µAVIN = VCC or GND
(Note 3) Supply Current
I
OZ
Maximum 3-STATE
5.5 ±0.25 ±2.5 µA
VI (OE) = VIL, V
IH
Leakage Current VI = VCC, GND
VO = VCC, GND
Loading...