Fairchild Semiconductor 74AC191SJX, 74AC191SJ, 74AC191SCX, 74AC191SC, 74AC191PC Datasheet
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© 1999 Fairchild Semiconductor Corporation DS009940 www.fairchildsemi.com
November 1988
Revised November 1999
74AC191 Up/Down Counter with Preset and Ripple Clock
74AC191
Up/Down Counter with Preset and Ripple Clock
General Description
The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous p resetting.
The preset featur e allows the AC191 to be us ed in programmable divider s. The C ount Enabl e input , the Terminal
Count output and the Rip ple Cloc k output m ake poss ible a
variety of methods of implem enting m ultista ge coun ters. In
the counting modes, state changes are i nitiated by the rising edge of the clock.
Features
■ ICC reduced by 50%
■ High speed—133 MHz typical count frequency
■ Synchronous counting
■ Asynchronous parallel load
■ Cascadable
■ Outputs source/sink 24 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC191SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74AC191SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC191MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC191PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
CE
Count Enable Input
CP Clock Pulse Input
P
0–P3
Parallel Data Inputs
PL
Asynchronous Parallel Load Input
U
/D
Up/Down Count Control Input
Q
0–Q3
Flip-Flop Outputs
RC
Ripple Clock Output
TC Terminal Count Output
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74AC191
RC T ruth T able
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
= Clock Pulse
Note 1: TC is generated internally
Functional Description
The AC191 is a synchronous up/down counter. The AC191
is organized as a 4-bit binary counter. It contains four edgetriggered flip-flops with internal gating and steering logic to
provide individual preset, count-up and count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desire d number.
When the Parallel Load (PL
) input is LOW, information
present on the Parallel Load inputs (P
0–P3
) is loaded into
the counter and appears on the Q outputs . This operatio n
overrides the counting functions, as indicated in the Mode
Select Table.
A HIGH signal on the CE
input inhibits counting. When CE
is LOW, internal state changes are initia ted synchro nously
by the LOW-to-HIGH transition of the clock input. The
direction of counti n g is d ete rmi n ed by th e U
/D input signal,
as indicated in the Mode Select Table. CE
and U/D can be
changed with the clo ck in either state, provided only th at
the recommended setup and hold times are observed.
Two types of outputs are pro vided as overflow/underflow
indicators. The terminal count (TC) output is normally
LOW. It goes HIGH when the circuits reach zero in the
count down mode or 15 in the cou nt up mode . The TC output will then remain HIGH until a state change occurs,
whether by counting o r presetting or u ntil U
/D is changed.
The TC output should not be used as a clock signal
because it is subject to decoding spikes.
The TC signal is also use d internally to enable the Ripple
Clock (RC
) output. The RC output is normally HIGH. When
CE
is LOW and TC is HIGH, RC output will go LOW when
the clock next goes LOW and will stay LOW until the clock
goes HIGH again. This feature simplifies the design of multistage counters, as indi cated in Figure 1 a nd Figure 2. In
Figure 1, each RC
output is used as the clock input for the
next higher stage. T his configurati on is partic ularly advantageous when the clo ck so ur ce has a limited drive ca pa bil ity, since it drives only the first stage. To prevent counting in
all stages it is only necessary to inhibit the first stage, since
a HIGH signal on CE
inhibits the RC output pulse, as indi-
cated in the RC
Truth Table. A disadvantage of this config uration, in some applicat ions, is the timing skew between
state changes in the f irst and last stages . This represents
the cumulative delay of the clock as it ripples through the
preceding stages.
A method of causing state changes to occur simultaneously in all stages is shown in Figur e 2. All clock inputs
are driven in pa rallel and the RC
outputs propagate the
carry/borrow signals in ripple fashion. In this configuration
the LOW state duration of the clock must be long enough to
allow the negative -go i ng edg e o f th e carry/borrow signal to
ripple through to the last stage before the clock goes HIGH.
There is no such restriction on t he HIGH state duration of
the clock, since the RC
output of any device goe s HIGH
shortly after its CP input goes HIGH.
The configuration shown in Figure 3 avoids ripple delays
and their associat ed restrictio ns. The CE
input for a given
stage is formed by combini ng the TC signals from all the
preceding stages. Note that in order to inhibit countin g an
enable signal must be in cluded in each carry gate. The
simple inhibit scheme of Figure 1 and Figure 2 doesn't
apply, because the TC output of a given stage is not
affected by its own CE
.
Mode Select Table
State Diagram
Inputs Outputs
PL CE TC
(Note 1)
CP RC
H L H
H H X X H
H X L X H
L X X X H
Inputs Mode
PL
CE U/D CP
H L L
Count Up
H L H
Count Down
L X X X Preset (Asyn.)
H H X X No Change (Hold)
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74AC191
Functional Description (continued)
FIGURE 1. N-Stage Counter Using Ripple Clock
FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow
FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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