Fairchild Semiconductor 74ABT374CSJX, 74ABT374CSJ, 74ABT374CSCX, 74ABT374CSC, 74ABT374CPC Datasheet

© 1999 Fairchild Semiconductor Corporation DS011510 www.fairchildsemi.com

November 1992
Revised November 1999

74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs

74ABT374
Octal D-Type Flip-Flop with 3-ST ATE Outputs

General Description

The ABT374 is an octal D-typ e flip-flop featuring separate
D-type inputs for each flip-flop and 3-STATE outputs for
bus-oriented applicatio ns. A buffered Clock (CP) and Out­put Enable (OE

) are common to all flip-flops.

Features

■ Edge-triggered D-type inputs

■ Buffered positive edge-triggered cl ock

■ 3-STATE outputs for bus-oriented applications

■ Output sink capability of 64 mA, source capability of

32 mA

■ Guaranteed output skew

■ Guaranteed multiple output switching specifications

■ Output switching sp ecified for both 50 pF and 250 pF

loads

■ Guaranteed simultaneous switching, noise level and
dynamic threshold performan ce

■ Guarante ed latchup pr otection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

74ABT374CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT374CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT374CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D

0–D7

Data Inputs
CP Clock Pulse Input (Active Rising Edge)
OE

3-STATE Output Enable Input (Active LOW)
O

0–O7

3-STATE Outputs

www.fairchildsemi.com 2

74ABT374

Functional Description

The ABT374 consi sts of ei gh t e dge -tr igge re d flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Outp ut Enable are com mon to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE

) LOW, the contents of the

eight flip-flops ar e available at the outputs. When OE

is
HIGH, the outputs are in a high impeda nce state. Opera­tion of the OE

input does not affect t he state of the flip-

flops.

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance



= LOW-to-HIGH Transition

NC = No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Internal Outputs Function

OE CP D Q O

H H L NC Z Hold
H H H NC Z Hold
H



L L Z Load

H



H H Z Load

L



L L L Data Available

L



H H H Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data

3 www.fairchildsemi.com

74ABT374

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.

Note 2: Either voltage lim it or c urrent limit is sufficient to protect inputs

DC Electrical Characteristics

Note 3: For 8-bit toggling, I

CCD

<0.8 mA/MHz.

Note 4: Guaranteed, but not tested.

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to

Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State −0.5V to 5.5V

in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the r ated I

OL

(mA)

DC Latchup Source Current:

OE

Pin

−150 mA
(Across Comm Operating Range)
Other Pins −500 mA

Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100mV/ns

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH Voltage 2.5 V Min IOH = −3 mA

2.0 V Min IOH = −32 mA
V

OL

Output LOW Voltage 0.55 V Min IOL = 64 mA

I

IH

Input HIGH Current 1

µA Max

VIN = 2.7V (Note 4)

1V

IN

= V

CC

I

BVI

Input HIGH Current Breakdown Test 7 µA MaxVIN = 7.0V

I

IL

Input LOW Current −1

µA Max

VIN = 0.5V (Note 4)

−1V

IN

= 0.0V

V

ID

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA, All Other Pins Grounded

I

OZH

Output Leakage Current 10 µA 0 − 5.5V

V

OUT

= 2.7V; OE = 2.0V

I

OZL

Output Leakage Current −10 µA 0 − 5.5V

V

OUT

= 0.5V; OE = 2.0V

I

OS

Output Short-Circuit Current −100 −275 mA Max V

OUT

= 0.0V

I

CEX

Output High Leakage Current 50 µA MaxV

OUT

= V

CC

I

ZZ

Bus Drainage Test 100 µA 0.0V

OUT

= 5.5V; All Others VCC or GND

I

CCH

Power Supply Current 50 µA Max All Outputs HIGH

I

CCL

Power Supply Current 30 mA Max All Outputs LOW

I

CCZ

Power Supply Current 50 µA Max

OE = VCC; All Others at VCC or GND

I

CCT

Additional ICC/Input Outputs Enabled 2.5 mA VI = VCC − 2.1V

Outputs 3-STATE 2.5 mA Max Enable Input VI = VCC − 2.1V
Outputs 3-STATE 2.5 mA Data Input VI = VCC − 2.1V

All Others at VCC or GND

I

CCD

Dynamic I

CC

No Load mA/

Max

Outputs OPEN

(Note 4) 0.30

MHz

OE = GND, (Note 3)
One Bit Toggling, 50% Duty Cycle

www.fairchildsemi.com 4

74ABT374

DC Electrical Characteristics

(SOIC package)

Note 5: Max number of output s d ef ined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of output s d ef ined as (n). n − 1 data input s are driven 0V to 3V. One output HIGH. Guaranteed, but not te s te d.
Note 7: Max number of data inpu ts (n) swit chin g. n − 1 in pu ts swit chin g 0V t o 3V. Input-under-te st sw itchin g: 3V to thres hold (V

ILD

), 0V to threshold (V

IHD

).

Guaranteed, but not tested.

AC Electrical Characteristics

(SOIC and SSOP Package)

AC Operating Requirements

Symbol Parameter Min Typ Max Units

V

CC

Conditions

CL = 50 pF, RL = 500Ω

V

OLP

Quiet Output Maximum Dynamic V

OL

0.5 0.8 V 5.0 TA = 25°C (Note 5)

V

OLV

Quiet Output Minimum Dynamic V

OL

−1.3 −0.9 V 5.0 TA = 25°C (Note 5)

V

OHV

Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 6)

V

IHD

Minimum HIGH Level Dynamic Input Voltage 2.0 1.6 V 5.0 TA = 25°C (Note 7)

V

ILD

Maximum LOW Level Dynamic Input Voltage 1.3 0.8 V 5.0 TA = 25°C (Note 7)

Symbol Parameter

TA = +25°C

T

A

= −55°C to

+125°C

T

A

= −40°C to +85°C

Units

V

CC

= +5.0V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

f

MAX

Maximum Clock Frequency 150 200 150 150 MHz

t

PLH

Propagation Delay 2.0 3.2 5.0 1.4 6.6 2.0 5.0

ns

t

PHL

CP to O

n

2.0 3.3 5.0 2.0 7.6 2.0 5.0

t

PZH

Output Enable Time 1.5 3.1 5.3 0.8 5.7 1.5 5.3

ns

t

PZL

1.5 3.1 5.3 1.5 7.2 1.5 5.3

t

PHZ

Output Disable Time 1.5 3.6 5.4 1.3 7.2 1.5 5.4

ns

t

PLZ

1.5 3.4 5.4 1.0 7.0 1.5 5.4

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = −40°C to +85°C

Units

V

CC

= +5.0V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Max Min Max Min Max

tS(H) Setup Time, HIGH 1.5 2.5 1.0

ns

t

S

(L) or LOW Dn to CP 1.5 2.5 1.5

tH(H) Hold Time, HIGH 1.0 2.5 1.0

ns

t

H

(L) or LOW Dn to CP 1.0 2.5 1.0

t

W

(H) Pulse Width, CP 3.0 3.3 3.0

ns

tW(L) HIGH or LOW 3.0 3.3 3.0