Fairchild NM93C06 service manual

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February 2000

(MICROWIRE

NM93C06 256-Bit Serial CMOS EEPROM

NM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus)

General Description

NM93C06 is a 256-bit CMOS non-volatile EEPROM organized as 16 x 16-bit array. This device features MICROWIRE interface which is a 4-wire serial bus with chipselect (CS), clock (SK), data input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors. There are 7 instructions implemented on the NM93C06 for various Read, Write, Erase, and Write Enable/Disable operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption.

“LZ” and “L” versions of NM93C06 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space considerations.

Functional Diagram

Features

■ Wide VCC 2.7V - 5.5V

■ Typical active current of 200µA

10µA standby current typical 1µA standby current typical (L)

0.1µA standby current typical (LZ)

■ No Erase instruction required before Write instruction

■ Self timed write cycle

■ Device status during programming cycles

■ 40 year data retention

■ Endurance: 1,000,000 data changes

■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

Synchronous Bus)

INSTRUCTION

DECODER

CONTROL LOGIC

16 BITS

AND CLOCK

GENERATORS

HIGH VOLTAGE

GENERATOR

AND

PROGRAM

TIMER

INSTRUCTION

ADDRESS

DECODER

EEPROM ARRAY

READ/WRITE AMPS

DATA IN/OUT REGISTER

DATA OUT BUFFER

NM93C06 Rev. E

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Connection Diagram

Dual-In-Line Package (N)

8–Pin SO (M8) and 8–Pin TSSOP (MT8)

(MICROWIRE

NM93C06 256-Bit Serial CMOS EEPROM

Synchronous Bus)

GND

Top View

Package Number

N08E, M08A and MTC08

Pin Names

CS Chip Select

SK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

GND Ground

NC No Connect

NOTE: Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the VCC applied to the device. This will ensure proper operation.

Power Supply

Ordering Information

NM 93 C XX LZ E XXX Letter Description

Package N 8-pin DIP

Temp. Range None 0 to 70°C

Voltage Operating Range Blank 4.5V to 5.5V

Density 06 256 bits

Interface 93 MICROWIRE

M8 8-pin SO MT8 8-pin TSSOP

V -40 to +125°C E -40 to +85°C

L 2.7V to 5.5V LZ 2.7V to 5.5V and

<1µA Standby Current

C CMOS CS Data protect and sequential

read

Fairchild Memory Prefix

NM93C06 Rev. E

www.fairchildsemi.com

(MICROWIRE

NM93C06 256-Bit Serial CMOS EEPROM

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C

All Input or Output Voltages +6.5V to -0.3V

with Respect to Ground

Lead Temperature

(Soldering, 10 sec.) +300°C

Operating Conditions

Ambient Operating Temperature

NM93C06 0°C to +70°C NM93C06E -40°C to +85°C NM93C06V -40°C to +125°C

Power Supply (V

) 4.5V to 5.5V

ESD rating 2000V

DC and AC Electrical Characteristics V

= 4.5V to 5.5V unless otherwise specified

Symbol Parameter Conditions Min Max Units

CCA

CCS

OL1

OH1

OL2

OH2

SKH

SKL

SKS

CSS

DIS

CSH

DIH

Operating Current CS = VIH, SK=1.0 MHz 1 mA

Standby Current CS = V

Input Leakage VIN = 0V to V

50 µA

±-1 µA

Output Leakage (Note 2)

Input Low Voltage -0.1 0.8 V Input High Voltage 2 VCC +1

Output Low Voltage IOL = 2.1 mA 0.4 V Output High Voltage IOH = -400 µA 2.4

Output Low Voltage IOL = 10 µA 0.2 V Output High Voltage IOH = -10 µAV

- 0.2

SK Clock Frequency (Note 3) 1 MHz

SK High Time 0°C to +70°C 250 ns

-40°C to +125°C 300

SK Low Time 250 ns

SK Setup Time 50 ns

Minimum CS Low Time (Note 4) 250 ns

CS Setup Time 100 ns

DO Hold Time 70 ns

DI Setup Time 100 ns

CS Hold Time 0 ns

DI Hold Time 20 ns

Output Delay 500 ns

CS to Status Valid 500 ns

CS to DO in Hi-Z CS = V

100 ns

Write Cycle Time 10 ms

Synchronous Bus)

NM93C06 Rev. E

www.fairchildsemi.com

(MICROWIRE

NM93C06 256-Bit Serial CMOS EEPROM

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C

All Input or Output Voltages +6.5V to -0.3V

with Respect to Ground

Lead Temperature

(Soldering, 10 sec.) +300°C

Operating Conditions

Ambient Operating Temperature

NM93C06L/LZ 0°C to +70°C NM93C06LE/LZE -40°C to +85°C NM93C06LV/LZV -40°C to +125°C

Power Supply (V

) 2.7V to 5.5V

ESD rating 2000V

DC and AC Electrical Characteristics V

= 2.7V to 5.5V unless otherwise specified

Symbol Parameter Conditions Min Max Units

CCA

CCS

SKH

SKL

SKS

CSS

DIS

CSH

DIH

Capacitance TA = 25°C, f = 1 MHz (Note 5)

Symbol Test Typ Max Units

OUT

Operating Current CS = VIH, SK=1.0 MHz 1 mA

Standby Current CS = V

L 10 µA LZ (2.7V to 4.5V) 1 µA

Input Leakage VIN = 0V to V Output Leakage (Note 2)

Input Low Voltage -0.1 0.15V Input High Voltage 0.8V

Output Low Voltage IOL = 10µA 0.1V Output High Voltage IOH = -10µA 0.9V

±1 µA

VCC +1

SK Clock Frequency (Note 3) 0 250 KHz

SK High Time 1 µs

SK Low Time 1 µs

SK Setup Time 0.2 µs

Minimum CS Low Time (Note 4) 1 µs

CS Setup Time 0.2 µs

DO Hold Time 70 ns

DI Setup Time 0.4 µs

CS Hold Time 0 ns

DI Hold Time 0.4 µs

Output Delay 2 µs

CS to Status Valid 1 µs

CS to DO in Hi-Z CS = V

0.4 µs

Write Cycle Time 15 ms

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Output Capacitance 5 pF

Input Capacitance 5 pF

Note 2: Typical leakage values are in the 20nA range.

Note 3: The shortest allowable SK clock period = 1/f

SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both t allowable to set 1/fSK = t

Note 4: CS (Chip Select) must be brought low (to V device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

SKHminimum

+ t

SKLminimum

(as shown under the fSK parameter). Maximum

and t

limits must be observed. Therefore, it is not

SKH

SKL

for shorter SK cycle time operation.

) for an interval of tCS in order to reset all internal

AC Test Conditions

VCC Range VIL/V

Input Levels Timing Level Timing Level

2.7V ≤ VCC ≤ 5.5V 0.3V/1.8V 1.0V 0.8V/1.5V ±10µA

(Extended Voltage Levels)

4.5V ≤ VCC ≤ 5.5V 0.4V/2.4V 1.0V/2.0V 0.4V/2.4V 2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (CL = 100 pF)

VIL/V

VOL/V

IOL/I

Synchronous Bus)

NM93C06 Rev. E

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