Fairchild NDT454P service manual
NDT454P
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
June 1996
Power SOT P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
-5.9A, -30V. R
R
R
High density cell design for extremely low R
High power and current handling capability in a widely used
surface mount package.
= 0.05Ω @ VGS = -10V
DS(ON)
= 0.07Ω @ VGS = -6V
DS(ON)
= 0.09Ω @ VGS = -4.5V.
DS(ON)
DS(ON).
fast switching, low in-line power loss, and resistance to
transients are needed.
____________________________________________________________________________________________
D
D S
G
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDT454P Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) ±5.9 A
- Pulsed ±15
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.3
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT454P Rev. D2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VDS = -24 V, V
VDS = -15 V, V
= 0 V
GS
= 0 V TJ = 70°C -5 µA
GS
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
-1 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage
Static Drain-Source On-Resistance
VDS = VGS, ID = -250 µA
VGS = -10 V, ID = -5.9 A
-1 -2.7 V
0.038 0.05
Ω
VGS = -6 V, ID = -5.2 A 0.046 0.07
0.064 0.09
-5
I
g
D(on)
FS
VGS = -4.5 V, ID = -4.6 A
On-State Drain Current VGS = -10 V, VDS = -5 V -15 A
VGS = -4.5, VDS = -5V
Forward Transconductance VDS = 15 V, ID = 5.9 A 10 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 610 pF
VDS = 15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 220 pF
950 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 18 60 ns
VDD = -15 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 80 120 ns
Turn - Off Fall Time 45 100 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 3
Gate-Drain Charge 11
VDS = -15 V,
ID = -5.9 A, VGS = -10 V
10 30 ns
29 40 nC
NDT454P Rev. D2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Drain-Source Diode Forward Current -1.9 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
T
J−TA
θJA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
=
(t)
R
θJC+RθCA
2
= I
(t) ×R
DS(ON ) T
D
(t)
J
1a
VGS = 0 V, IS = -5.9 A
(Note 2)
VGS = 0V, IF = -5.9 A, dIF/dt = 100 A/µs
1b
1c
-0.85 -1.3 V
100 ns
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT454P Rev. D2
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