Fairchild NDT452AP service manual
NDT452AP
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
June 1996
Power SOT P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and DC motor
-5A, -30V. R
R
High density cell design for extremely low R
= 0.065Ω @ VGS = -10V
DS(ON)
= 0.1Ω @ VGS = -4.5V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
control.
________________________________________________________________________________
D
D S
G
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDT452AP Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) -5 A
- Pulsed - 15
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.3
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT452AP Rev. B1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
TJ = 55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.6 -2.8 V
-0.7 -1.2 -2.2
0.052 0.065
Static Drain-Source On-Resistance
TJ = 125°C
VGS = -10 V, ID = -5.0 A
Ω
TJ = 125°C 0.075 0.13
0.085 0.1
-5
I
g
D(on)
VGS = -4.5 V, ID = -4.3 A
On-State Drain Current VGS = -10 V, VDS = -5 V -15 A
VGS = -4.5 V, VDS = -5 V
FS
Forward Transconductance VDS = -10 V, ID = -5.0 A 7 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 430 pF
VDS = -15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 160 pF
690 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 20 30 ns
VDD = -10 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 40 50 ns
Turn - Off Fall Time 19 40 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 3.2 nC
Gate-Drain Charge 5.2 nC
VDS = -10 V,
ID = -5.0 A, VGS = -10 V
9 20 ns
22 30 nC
NDT452AP Rev. B1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
θ
design while R
P
D
Typical R
Maximum Continuous Drain-Source Diode Forward Current -2.5 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -2.5 A
(Note 2)
-0.85 -1.2 V
Reverse Recovery Time VGS = 0 V, IF = -2.5 A, dIF/dt = 100 A/µs 100 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
(t)
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
1a
T
J−TA
θJA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
=
(t)
R
θJC+RθCA
2
= I
(t) ×R
DS(ON ) T
D
(t)
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT452AP Rev. B1
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