Fairchild NDT3055L service manual
August 1998
NDT3055L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance and provide superior
switching performance, and withstand high energy pulse
in the avalanche and commutation modes. These devices
are particularly suited for low voltage applications such as
DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to
transients are needed.
SuperSOTTM-3
D
SuperSOTTM-6
SuperSOTTM-8 SO-8
D
S
SOT-223
D
G
G
D S
4 A, 60 V. R
R
= 0.100 Ω @ VGS = 10 V,
DS(ON)
= 0.120 Ω @ VGS = 4.5 V.
DS(ON)
Low drive requirements allowing operation directly from logic
drivers. V
High density cell design for extremely low R
GS(TH)
< 2V.
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
SOT-223
D
SOIC-16
D
S
SOT-223
(J23Z)
G
*
G
S
Absolute Maximum Ratings T
= 25oC unless otherwise noted
A
Symbol Parameter NDT3055L Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 60 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a) 4 A
- Pulsed 25
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.3
1.1
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
© 1998 Fairchild Semiconductor Corporation
NDT3055L Rev.A1
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = 250 µA, Referenced to 25 o C
VDS = 60 V, V
GS
= 0 V
55
1 µA
mV/o C
TJ =125°C 50 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC -4 mV /oC
/∆T
J
VDS = VGS, ID = 250 µA
Static Drain-Source On-Resistance VGS = 10 V, ID = 4 A 0.07 0.1
TJ =125°C
1 1.6 2 V
Ω
0.125 0.18
VGS = 4.5 V, ID = 3.7 A 0.103 0.12
I
D(ON)
g
On-State Drain Current
FS
Forward Transconductance VDS = 5 V, ID = 4 A 7 S
VGS = 5 , VDS = 10 V
10 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 110 pF
VDS = 25, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 30 pF
345 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 7.5 20 ns
VDD = 25, ID = 1 A,
VGS = 10 V, R
GEN
= 6 Ω
Turn - Off Delay Time 20 50 ns
Turn - Off Fall Time 7 20 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.7 nC
Gate-Drain Charge 3.2 nC
VDS = 40 V, ID = 4 A,
VGS = 10 V
5 20 ns
13 20 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
guaranteed by design while R
Maximum Continuous Drain-Source Diode Forward Current 2.5 A
Drain-Source Diode Forward Voltage
is determined by the user's board design.
CA
θ
VGS = 0 V, IS = 2.5 A
(Note 2)
0.8 1.2 V
JC
θ
is
a. 42oC/W when mounted on a 1 in2 pad of
2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
b. 95oC/W when mounted on a 0.066 in
pad of 2oz Cu.
2
c. 110oC/W when mounted on a 0.00123
2
in
pad of 2oz Cu.
NDT3055L Rev.A1
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