Fairchild NDT3055 service manual
May 1998
NDT3055
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high
density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for
low voltage applications such as DC motor control and
DC/DC conversion where fast switching, low in-line
power loss, and resistance to transients are needed.
SuperSOTTM-3
D
SuperSOTTM-6
SuperSOTTM-8
D
S
D
SOT-223
G
G
D S
4 A, 60 V. R
High density cell design for extremely low R
= 0.100 Ω @ VGS = 10 V.
DS(ON)
DS(ON)
High power and current handling capability in a widely used
surface mount package.
SO-8
SOT-223
D
S
G
G
SOT-223*
(J23Z)
.
SOIC-16
D
S
Absolute Maximum Ratings T
= 25oC unless otherwise noted
A
Symbol Parameter NDT3055 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 60 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a) 4 A
- Pulsed 25
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.3
1.1
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
© 1998 Fairchild Semiconductor Corporation
NDT3055 Rev.B
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = 250 µA, Referenced to 25 o C
VDS = 48 V, V
GS
= 0 V
63
10 µA
mV/o C
TJ =125°C 100 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
2 3 4 V
TJ =125°C 1.5 2.4 3
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 4 A
0.084 0.1
Ω
TJ =125°C 0.14 0.18
I
D(ON)
g
On-State Drain Current
FS
Forward Transconductance VDS = 15 V, ID = 4 A 6 S
VGS = 10 V, VDS = 10 V
15 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 100 pF
VDS = 30 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 30 pF
250 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 25 V, ID = 1.2 A,
Turn - On Rise Time 18 50 ns
VGS = 10 V, R
GEN
= 50 Ω
10 25 ns
Turn - Off Delay Time 37 65 ns
Turn - Off Fall Time 30 60 ns
Total Gate Charge VDS = 40 V, ID = 4 A,
Gate-Source Charge 2.3 nC
VGS = 10 V
9 15 nC
Gate-Drain Charge 2.6 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
guaranteed by design while R
Typical R
Maximum Continuous Drain-Source Diode Forward Current 2.5 A
Drain-Source Diode Forward Voltage
is determined by the user's board design.
CA
using the board layouts shown below on FR-4 PCB in a still air environment:
JA
θ
θ
VGS = 0 V, IS = 2.5 A
(Note 2)
0.85 1.2 V
is
JC
θ
a. 42oC/W when mounted on a 1 in2 pad of
2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
b. 95oC/W when mounted on a 0.066 in
pad of 2oz Cu.
2
c. 110oC/W when mounted on a 0.00123
2
in
pad of 2oz Cu.
NDT3055 Rev.B
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