Fairchild NDT014 service manual
NDT014
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
September 1996
Power SOT N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
2.7A, 60V. R
High density cell design for extremely low R
= 0.2Ω @ VGS = 10V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
suited for low voltage applications such as DC motor control
and DC/DC conversion where fast switching, low in-line power
loss, and resistance to transients are needed.
_________________________________________________________________________________________________________
D
G
D S
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDT014 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 60 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) ±2.7 A
- Pulsed ±10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT014 Rev. C1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VDS = 60 V, V
VDS = 48 V, V
= 0 V
GS
= 0 V, TJ=125°C 250 µA
GS
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
25 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
g
GS(th)
DS(ON)
FS
Gate Threshold Voltage
Static Drain-Source On-Resistance
Forward Transconductance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 1.6 A
VDS = 25 V, ID = 1.6 A
2 3 4 V
0.18 0.2
2 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 60 pF
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 15 pF
155 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD =30 V, ID = 10 A,
V
= 10 V, R
Turn - On Rise Time 64 100 ns
GEN
GEN
= 24 Ω
10 20 ns
Turn - Off Delay Time 10 20 ns
Turn - Off Fall Time 10 20 ns
Total Gate Charge VDS = 48 V,
Gate-Source Charge 1.2 3.1 nC
ID = 10 A, VGS = 10 V
5 11 nC
Gate-Drain Charge 2 5.8 nC
NDT014 Rev. C1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
t
rr
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Drain-Source Diode Forward Current 2.7 A
Maximum Pulsed Drain-Source Diode Forward Current 22 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.7A
Reverse Recovery Time
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJ A
θJ C+RθCA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
2
= I
(t) × R
DS(O N ) T
D
(t)
J
1a
VGS = 0 V, IF = 10 A, dIF/dt = 100 A/µs
1b
(Note 2) 0.95 1.6 V
1c
140 ns
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT014 Rev. C1
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