Fairchild NDS9952A service manual

NDS9952A

Dual N & P-Channel Enhancement Mode Field Effect Transistor

General Description Features

February 1996

These dual N- and P-channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
notebook computer power management and other

N-Channel 3.7A, 30V, R
P-Channel -2.9A, -30V, R

High density cell design or extremely low R

=0.08Ω @ V

DS(ON)

=0.13Ω @ V

DS(ON)

=10V.

GS

=-10V.

GS

.

DS(ON)

High power and current handling capability in a widely used
surface mount package.

Dual (N & P-Channel) MOSFET in surface mount package.

battery powered circuits where fast switching, low in-line
power loss, and resistance to transients are needed.

________________________________________________________________________________

5

6

7

8

4

3

2

1

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter N-Channel P-Channel Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 -30 V

Gate-Source Voltage ± 20 ± 20 V

Drain Current - Continuous (Note 1a) ± 3.7 ± 2.9 A

- Pulsed ± 15 ± 10

P

D

Power Dissipation for Dual Operation 2 W

Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

θ

R

θ

© 1997 Fairchild Semiconductor Corporation

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W

JA

Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

JC

NDS9952A.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS

BV

I

DSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 30 V

VGS = 0 V, ID = -250 µA

Zero Gate Voltage Drain Current VDS = 24 V, V

= 0 V N-Ch 2 µA

GS

P-Ch -30 V

TJ = 55°C 25 µA
P-Ch -2 µA

TJ = 55°C

-25 µA

All -100 nA

I

GSSF

I

GSSR

VDS = -24 V, V

GS

= 0 V

Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage VDS = VGS, ID = 250 µA N-Ch 1 1.7 2.8 V

TJ = 125°C 0.7 1.2 2.2

P-Ch -1 -1.6 -2.8

-0.85 -1.25 -2.5

N-Ch 0.06 0.08

0.08 0.13

0.08 0.11

R

DS(ON)

Static Drain-Source On-Resistance

VDS = VGS, ID = -250 µA

TJ = 125°C

VGS = 10 V, ID = 1.0 A

TJ = 125°C

VGS = 4.5 V, ID = 0.5 A

TJ = 125°C 0.11 0.18

VGS = -10 V, ID = -1.0 A

TJ = 125°C

P-Ch 0.11 0.13

0.15 0.21

VGS = -4.5 V, ID = -0.5 A 0.17 0.2

TJ = 125°C 0.24 0.32

I

D(on)

On-State Drain Current

VGS = 10 V, VDS = 5 V

N-Ch 15 A

VGS = -10 V, VDS = -5 V P-Ch -10

g

FS

Forward Transconductance

VDS = 15 V, ID = 3.7 A

N-Ch 6 S

VDS = -15 V, ID = -2.9 A P-Ch 4

DYNAMIC CHARACTERISTICS

C

iss

Input Capacitance N-Channel

VDS = 10 V, VGS = 0 V,
f = 1.0 MHz

C

oss

C

rss

Output Capacitance N-Ch 225 pF

P-Channel

Reverse Transfer Capacitance N-Ch 85 pF

VDS = -10 V, VGS = 0 V,
f = 1.0 MHz

N-Ch 320 pF
P-Ch 350

P-Ch 260

P-Ch 100

Ω

NDS9952A.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Type Min Typ Max Units
SWITCHING CHARACTERISTICS (Note 2)

t

t

t

t

D(on)

r

D(off)

f

Turn - On Delay Time N-Channel

VDD = 10 V, ID = 1 A,
V

= 10 V, R

Turn - On Rise Time N-Ch 13 20 ns

GEN

GEN

= 6 Ω

P-Channel

Turn - Off Delay Time N-Ch 21 50 ns

VDD = -10 V, ID = -1 A,
V

= -10 V, R

GEN

GEN

= 6 Ω

N-Ch 10 15 ns
P-Ch 9 40

P-Ch 21 40

P-Ch 21 90

Turn - Off Fall Time N-Ch 5 50 ns

P-Ch 8 50

Q

g

Q

gs

Q

gd

Total Gate Charge N-Channel

VDS = 10 V,
ID = 3.7 A, VGS = 10 V

N-Ch 9.5 27 nC
P-Ch 10 25

Gate-Source Charge N-Ch 1.5 nC

P-Channel

Gate-Drain Charge N-Ch 3.3 nC

VDS = -10 V,
ID = -2.9 A, VGS = -10 V

P-Ch 1.6

P-Ch 3.4

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

Maximum Continuous Drain-Source Diode Forward Current N-Ch 1.2 A

P-Ch -1.2

V

SD

t

rr

Notes:

1. R

P

design while R

D

Typical R

Drain-Source Diode Forward
Voltage

VGS = 0 V, IS = 1.25 A
VGS = 0 V, IS = -1.25 A

(Note 2) N-Ch 0.8 1.3 V

(Note 2)

P-Ch -0.8 -1.3

Reverse Recovery Time VGS = 0 V, IF = 1.25 A, dIF/dt = 100 A/µs N-Ch 75 ns

VGS = 0 V, IF = -1.25 A, dIF/dt = 100 A/µs

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

=

R

θ

a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.

b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.

c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.

T

J−TA

=

(t)

R

θJ A

θJ C+RθCA

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

1a

J−TA

2

= I

(t) × R

DS(ON ) T

D

(t)

J

1b

P-Ch 100

1c

is guaranteed by

JC

θ

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDS9952A.SAM