May 1998
NDS9945
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to provide superior switching
performance and minimize on-state resistance. These
devices are particularly suited for low voltage applications
such as disk drive motor control, battery powered circuits
where fast switching, low in-line power loss, and resistance
to transients are needed.
3.5 A, 60 V. R
R
High density cell design for extremely low R
High power and current handling capability in a widely
used surface mount package.
Dual MOSFET in surface mount package.
= 0.100 Ω @ VGS = 10 V,
DS(ON)
= 0.200 Ω @ VGS = 4.5 V.
DS(ON)
DS(ON)
.
SOT-23
SuperSOTTM-6
D2
SuperSOTTM-8
SO-8 SOT-223
5
SOIC-16
4
D2
D1
D1
NDS
6
3
9945
G2
7
S2
SO-8
pin
Absolute Maximum Ratings T
Symbol Parameter NDS9945 Units
V
DSS
V
GSS
I
D
P
D
TJ,T
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Drain-Source Voltage 60 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) 3.5 A
- Pulsed 10
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
G1
1
S1
= 25oC unless other wise noted
A
8
2
1
© 1998 Fairchild Semiconductor Corporation
NDS9945 Rev.B
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
DSS
∆BV
DSS
I
DSS
I
GSSF
I
GSSR
ON CHARACTERISTICS
V
GS(th)
R
DS(ON)
I
D(ON)
g
FS
Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA 60 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
I
= 250 µA, Referenced to 25 oC
D
V
= 48 V, V
DS
GS
= 0 V
60
1 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
(Note 2)
V
= -20 V, VDS= 0 V
GS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.7 3 V
=125°C
T
J
0.7 2.2
Static Drain-Source On-Resistance VGS = 10 V, I D = 3.5 A 0.076 0.1
TJ =125°C
= 4.5 V, I D = 2.5 A 0.103 0.2
V
GS
=125°C
T
J
0.124 0.18
0.166 0.3
On-State Drain Current VGS = 10 V, VDS = 10 V 10 A
Forward Transconductance
V
= 10 V, I D = 3.5 A
DS
5.3 S
mV/ oC
-100 nA
Ω
DYNAMIC CH ARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 25 V, VGS = 0 V,
Output Capacitance 110 pF
Reverse Transfer Capacitance 25 pF
SWITCHING CHARACTERISTICS
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time 20 50
Turn - Off Fall Time 7 40
Total Gate Charge VDS = 30 V, I D = 3.5 A, 12.9 30 nC
Gate-Source Charge
Gate-Drain Charge 3.2
(Note 2)
f = 1.0 MHz
V
= 30 V, I D = 1 A
DS
V
= 10 V , R
GS
V
= 10 V
GS
GEN
= 6 Ω
345 pF
5 25 ns
7.5 30
1.7
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
I
rr
Notes:
1. R
design while R
JA
θ
Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Current 1.5 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
V
= 0 V, I S = 1.3 A
GS
V
= 0 V, IF = 1.3 A,
GS
dI
/dt = 100 A/µs
F
(Note 2)
0.8 1.2 V
40 ns
is guaranteed by
JC
θ
a. 78OC/W on a 0.5 in
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
2
b. 125OC/W on a 0.02 in
pad of 2oz copper.
2
c. 135OC/W on a 0.003 in
pad of 2oz copper.
2
NDS9945 Rev.B
Typical Electrical Characteristics
20
15
10
V = 10V
GS 6.0V
5.0V
4.5V
4.0V
3.5V
5
D
I , DRAIN-SOURCE CURRENT (A)
0
0 1 2 3 4 5
V , DRAIN-SOURCE VOLTAGE (V)
DS
Figure 1. On-Region Characteristics.
2
I = 3.5A
D
1.8
V = 10V
GS
1.6
1.4
1.2
1
DS(ON)
0.8
R , NORMALIZED
0.6
DRAIN-SOURCE ON-RESISTANCE
0.4
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
3.0V
2.5
V = 3.0V
GS
2.25
2
1.75
1.5
1.25
DS(ON)
R , NORMALIZED
1
DRAIN-SOURCE ON-RESISTANCE
0.75
0 2 4 6 8 10
3.5 V
4.0 V
4.5 V
I , DRAIN CURRENT (A)
D
5.0V
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.4
0.3
0.2
0.1
DS(ON)
R , ON-RESISTANCE (OHM)
0
2 4 6 8 10
V , GATE TO SOURCE VOLTAGE (V)
GS
T =125°C
A
T =25°C
A
6.0V
10V
I = 2A
D
Figure 3. On-Resistance Variation With
Temperature.
10
V = 5V
DS
8
6
4
D
I , DRAIN CURRENT (A)
2
0
1 1.5 2 2.5 3 3.5 4 4.5 5
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 5 . Transfer Characteristics.
T = -55°C
J
25°C
125°C
Figure 4. On Resistance Variation with
Gate-to-Source Voltage.
10
V = 0V
GS
5
3
2
1
0.5
0.3
0.2
S
I , REVERSE DRAIN CURRENT (A)
0.1
0.4 0.6 0.8 1 1.2
T = 125°C
J
25°C
-55°C
V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
NDS9945 Rev.B
Typical Electrical Characteristics (continued)
10
8
I = 3.5A
D
V = 10V
DS
40V
6
4
2
GS
V , GATE-SOURCE VOLTAGE (V)
0
0 2 4 6 8 10 12 14
Q , GATE CHARGE (nC)
g
Figure 7. Gate Charge Characteristics.
30
10
3
RDS(ON) LIMIT
1
0.3
V =10V
0.1
D
I , DRAIN CURRENT (A)
0.03
0.01
GS
SINGLE PULSE
R = 135°C/W
JA
θ
A
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 20 50 100
V , DRAIN-SOURCE VOLTAGE (V)
DS
DC
1ms
10ms
100ms
1s
10s
30V
100us
1000
400
200
100
50
CAPACITANCE (pF)
f = 1 MHz
20
V = 0 V
GS
10
0.1 0.3 1 3 10 20 50
V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
iss
C
oss
C
rss
Figure 8. Capacitance Characteristics.
50
40
30
20
POWER (W)
10
0
0.001 0.01 0.1 1 10 100 300
SINGLE PULSE TIME (SEC)
SINGLE PULSE
R =135°C/W
JA
θ
T = 25°C
A
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
D = 0.5
0.5
R (t) = r(t) * R
0.2
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.0001 0.001 0.01 0.1 1 10 100 300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
t , TIME (sec)
1
JA
θ
R =135 °C/W
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t /t
JA
θ
JA
θ
1 2
NDS9945 Rev.B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
2
E
CMOS
TM
FACT™
FACT Quiet Series™
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. E
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