Fairchild NDS9945 service manual
May 1998
NDS9945
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to provide superior switching
performance and minimize on-state resistance. These
devices are particularly suited for low voltage applications
such as disk drive motor control, battery powered circuits
where fast switching, low in-line power loss, and resistance
to transients are needed.
3.5 A, 60 V. R
R
High density cell design for extremely low R
High power and current handling capability in a widely
used surface mount package.
Dual MOSFET in surface mount package.
= 0.100 Ω @ VGS = 10 V,
DS(ON)
= 0.200 Ω @ VGS = 4.5 V.
DS(ON)
DS(ON)
.
SOT-23
SuperSOTTM-6
D2
SuperSOTTM-8
SO-8 SOT-223
5
SOIC-16
4
D2
D1
D1
NDS
6
3
9945
G2
7
S2
SO-8
pin
Absolute Maximum Ratings T
Symbol Parameter NDS9945 Units
V
DSS
V
GSS
I
D
P
D
TJ,T
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Drain-Source Voltage 60 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) 3.5 A
- Pulsed 10
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
G1
1
S1
= 25oC unless other wise noted
A
8
2
1
© 1998 Fairchild Semiconductor Corporation
NDS9945 Rev.B
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
DSS
∆BV
DSS
I
DSS
I
GSSF
I
GSSR
ON CHARACTERISTICS
V
GS(th)
R
DS(ON)
I
D(ON)
g
FS
Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA 60 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
I
= 250 µA, Referenced to 25 oC
D
V
= 48 V, V
DS
GS
= 0 V
60
1 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
(Note 2)
V
= -20 V, VDS= 0 V
GS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.7 3 V
=125°C
T
J
0.7 2.2
Static Drain-Source On-Resistance VGS = 10 V, I D = 3.5 A 0.076 0.1
TJ =125°C
= 4.5 V, I D = 2.5 A 0.103 0.2
V
GS
=125°C
T
J
0.124 0.18
0.166 0.3
On-State Drain Current VGS = 10 V, VDS = 10 V 10 A
Forward Transconductance
V
= 10 V, I D = 3.5 A
DS
5.3 S
mV/ oC
-100 nA
Ω
DYNAMIC CH ARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 25 V, VGS = 0 V,
Output Capacitance 110 pF
Reverse Transfer Capacitance 25 pF
SWITCHING CHARACTERISTICS
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time 20 50
Turn - Off Fall Time 7 40
Total Gate Charge VDS = 30 V, I D = 3.5 A, 12.9 30 nC
Gate-Source Charge
Gate-Drain Charge 3.2
(Note 2)
f = 1.0 MHz
V
= 30 V, I D = 1 A
DS
V
= 10 V , R
GS
V
= 10 V
GS
GEN
= 6 Ω
345 pF
5 25 ns
7.5 30
1.7
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
I
rr
Notes:
1. R
design while R
JA
θ
Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Current 1.5 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
V
= 0 V, I S = 1.3 A
GS
V
= 0 V, IF = 1.3 A,
GS
dI
/dt = 100 A/µs
F
(Note 2)
0.8 1.2 V
40 ns
is guaranteed by
JC
θ
a. 78OC/W on a 0.5 in
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
2
b. 125OC/W on a 0.02 in
pad of 2oz copper.
2
c. 135OC/W on a 0.003 in
pad of 2oz copper.
2
NDS9945 Rev.B
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