Fairchild NDS9400A service manual
February 1996
NDS9400A
Single P-Channel Enhancement Mode Field Effect Transistor
General Description Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
________________________________________________________________________________
-3.4A, -30V. R
High density cell design for extremely low R
= 0.13Ω @ V
DS(ON)
= -10V.
GS
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Rugged and reliable.
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
5
6
7
8
4
3
2
1
Symbol Parameter NDS9400A Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) ± 3.4 A
- Pulsed ± 10
P
D
Maximum Power Dissipation (Note 1a) 2.5 W
(Note 1b) 1.2
(Note 1c) 1
TJ,T
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
θ
R
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
JC
© 1997 Fairchild Semiconductor Corporation
NDS9400A.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
-2 µA
TJ = 55°C
-25 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.6 -2.8 V
-0.85 -1.25 -2.5
0.11 0.13
Static Drain-Source On-Resistance
TJ = 125°C
VGS = -10 V, ID = -1.0 A
Ω
TJ = 125°C 0.15 0.21
0.17 0.2
0.24 0.32
4 S
I
g
D(on)
VGS = -4.5 V, ID = -0.5 A
TJ = 125°C
On-State Drain Current VGS = -10 V, VDS = -5 V -10 A
FS
Forward Transconductance
VDS = -15 V, ID = -3.4 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -10 V, VGS = 0 V,
Output Capacitance 260 pF
f = 1.0 MHz
350 pF
Reverse Transfer Capacitance 100 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 21 40 ns
VDD = -10 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 21 90 ns
Turn - Off Fall Time 8 50 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.6 nC
Gate-Drain Charge 3.4 nC
VDS = -10 V,
ID = -3.4 A, VGS = -10 V
9 40 ns
10 25 nC
NDS9400A.SAM
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
I
rr
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Drain-Source Diode Forward Current -1.9 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -1.25 A
(Note 2)
-0.8 -1.3 V
Reverse Recovery Time VGS = 0 V, IF = -2.0 A, dIF/dt = 100 A/µs 100 ns
Reverse Recovery Current 1.9 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
−T
T
J
=
R
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 50oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz cpper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz cpper.
1a
−T
J
A
(t)
A
=
R
θ
J C
2
= I
(t) × R
DS (ON ) T
D
+R
(t)
θ
CA
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9400A.SAM
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