These Complementary MOSFET half bridge devices are
produced using Fairchild's proprietary, high cell density,
DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage half bridge
applications or CMOS applications when both gates are
connected together.
N-Channel 4.3A, 30V, R
P-Channel -3.4A, -30V, R
High density cell design or extremely low R
=0.08Ω @ V
DS(ON)
DS(ON)
=0.13Ω @ V
GS
GS
DS(ON)
=10V.
=-10V.
.
High power and current handling capability in a widely used
surface mount package.
Matched pair for equal input capacitance and power capability
.
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward CurrentN-Ch2.1A
P-Ch-2.1
V
SD
t
rr
Drain-Source Diode Forward
Voltage
VGS = 0 V, IS = 2.1 A
VGS = 0 V, IS = -2.1 A
Reverse Recovery TimeN-Channel
VGS = 0 V, IF = 2.1 A, dIF/dt = 100 A/µs
P-Channel
(Note 2)N-Ch0.81.2V
(Note 2)
P-Ch-0.8-1.2
N-Ch100ns
P-Ch100
VGS = 0 V, IF = -2.1 A, dIF/dt = 100 A/µs
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
design while R
(t)
P
D
Typical R
is determined by the user's board design.
CA
θ
T
−T
T
J
=
R
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 50oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz cpper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz cpper.