Fairchild NDS8434 service manual
NDS8434
Single P-Channel Enhancement Mode Field Effect Transistor
General Description Features
June 1996
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
-6.5A, -20V. R
R
High density cell design for extremely low R
= 0.035Ω @ V
DS(ON)
= 0.05Ω @ V
DS(ON)
= -4.5V
GS
= -2.7V.
GS
DS(ON).
High power and current handling capability in a widely used
surface mount package.
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
___________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS8434 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -20 V
Gate-Source Voltage -8 V
Drain Current - Continuous (Note 1a) -6.5 A
- Pulsed -20
P
T
D
J,TSTG
Maximum Power Dissipation (Note 1a) 2.5 W
(Note 1b)
(Note 1c)
1.2
1
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θ
R
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
JC
NDS8434 Rev. A3
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V
Zero Gate Voltage Drain Current
VDS = -16 V, V
GS
= 0 V
-1 µA
TJ = 55oC -10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 8 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-0.4 -0.7 -1 V
TJ = 125oC -0.3 -0.45 -0.8
R
I
g
D(on)
FS
DS(ON)
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = -4.5 V, ID = -6.5 A
TJ = 125oC
VGS = -2.7 V, ID = -5.5 A
VGS = -4.5 V, VDS = -5 V
VGS = -2.7 V, VDS = -5 V
VDS = -10 V, ID = -6.5 A
0.026 0.035
0.037 0.07
0.036 0.05
-15 A
-10
18 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 1070 pF
VDS = -10 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 360 pF
2330 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = -6 V, ID = -1 A,
V
= -4.5 V, R
Turn - On Rise Time 38 80 ns
GEN
GEN
= 6 Ω
20 40 ns
Turn - Off Delay Time 169 300 ns
Turn - Off Fall Time 63 120 ns
Total Gate Charge VDS = -5 V,
Gate-Source Charge 5.3 nC
ID = -6.5 A, VGS = -4.5 V
40 80 nC
Gate-Drain Charge 11 nC
NDS8434 Rev. A3
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current -2.1 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -2.1 A
(Note 2)
-0.8 -1.2 V
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
design while R
(t)
P
D
Typical R
Scale 1 : 1 on letter size paper
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 50oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper.
c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper.
T
J−TA
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
1a
J−TA
=
(t)
R
θ
J C
2
= I
(t) × R
DS(ON ) T
D
+R
(t)
θ
CA
J
1b
1c
is guaranteed by
JC
θ
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8434 Rev. A3
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