Fairchild NDS356AP service manual
NDS356AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
September 1996
SuperSOTTM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications such as notebook computer power management,
portable electronics, and other battery powered circuits where
fast high-side switching, and low in-line power loss are
needed in a very small outline surface mount package.
-1.1 A, -30 V, R
R
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
= 0.3 Ω @ VGS=-4.5 V
DS(ON)
= 0.2 Ω @ VGS=-10 V.
DS(ON)
DS(ON)
.
capability.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS356AP Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a) ±1.1 A
- Pulsed ±10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
θ
R
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
JC
NDS356AP Rev.C1
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
TJ =55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20V, VDS = 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-0.8 -1.6 -2.5 V
TJ =125°C -0.5 -1.3 -2.2
R
I
g
DS(ON)
D(ON)
FS
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = -4.5 V, ID = -1.1 A
VGS = -10 V, ID = -1.3 A
VGS = -4.5 V, VDS = -5 V
VDS = -5 V, I
= -1.1 A 2 S
D
TJ =125°C
0.25 0.3
0.35 0.4
0.14 0.2
-3 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -10 V, VGS = 0 V,
Output Capacitance 170 pF
f = 1.0 MHz
280 pF
Reverse Transfer Capacitance 65 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 17 30 ns
VDD = -10 V, ID = -1 A,
VGS = -10 V, R
GEN
= 50 Ω
Turn - Off Delay Time 53 90 ns
Turn - Off Fall Time 38 80 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 0.7 nC
Gate-Drain Charge 1.5 nC
VDS = -10 V, ID = -1.1 A,
VGS = -5 V
8 15 ns
3.4 4.4 nC
NDS356AP Rev.C1
Electrical Characteristics (T
TJ−
T
TJ−
T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Source Current -0.42 A
Maximum Pulsed Drain-Source Diode Forward Current -10 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
A
(t)
=
(t)
R
θJA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
=
R
θJC+RθCA
A
2
(t)
= I
× R
DS(ON)@T
D
(t)
J
VGS = 0 V, IS = -0.42 (Note 2)
-0.8 -1.2 V
is guaranteed by
JC
θ
1a
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
1b
NDS356AP Rev.C1
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