Fairchild NDS355AN service manual
NDS355AN
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
January 1997
SuperSOTTM-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
1.7A, 30 V, R
R
= 0.125 Ω @ VGS = 4.5 V
DS(ON)
= 0.085 Ω @ VGS = 10 V.
DS(ON)
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS355AN Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a) 1.7 A
- Pulsed 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
NDS355AN Rev.C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ =125°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 20 VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
D(ON)
g
GS(th)
DS(ON)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.6 2 V
0.5 1.2 1.5
0.105 0.125
0.16 0.23
0.065 0.085
6 A
3.5 S
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
TJ =125°C
VGS = 4.5 V, ID = 1.7 A
TJ =125°C
VGS = 10 V, ID = 1.9 A
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, ID= 1.7 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 135 pF
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 48 pF
195 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
d(on)
r
d(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 13 25 ns
VGS = 10 V, R
GEN
= 6 Ω
10 20 ns
Turn - Off Delay Time 13 25 ns
Turn - Off Fall Time 4 10 ns
Turn - On Delay Time VDD = 5 V, ID = 1 A,
Turn - On Rise Time 32 60 ns
VGS = 4.5 V, R
GEN
= 6 Ω
10 20 ns
Turn - Off Delay Time 10 20 ns
Turn - Off Fall Time 5 10 ns
Total Gate Charge VDS = 10 V, ID = 1.7 A,
Gate-Source Charge 0.8 nC
VGS = 5 V
3.5 5 nC
Gate-Drain Charge 1.7 nC
NDS355AN Rev.C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
design while R
P
Typical R
a. 250
Maximum Continuous Drain-Source Diode Forward Current 0.42 A
Maximum Pulsed Drain-Source Diode Forward Current 10 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS =0.42 A (Note 2) 0.8 1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
T
−T
T
J
(t)
=
R
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
−T
J
A
(t)
o
A
=
R
θ
J C
C/W when mounted on a 0.02 in2 pad of 2oz copper.
2
= I
(t) × R
DS (ON ) T
D
+R
(t)
θ
CA
J
is guaranteed by
JC
θ
1a
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
1b
NDS355AN Rev.C
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