Fairchild NDS351N service manual
NDS351N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
March 1996
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMCIA cards, and other
battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline
surface mount package.
1.1A, 30V. R
= 0.25Ω @ VGS = 4.5V.
DS(ON)
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS351N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous 20 V
Maximum Drain Current - Continuous (Note 1a) ± 1.1 A
- Pulsed ± 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient
(Note 1a)
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
250 °C/W
NDS351N Rev. E2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current
VDS = 24 V, V
GS
= 0 V
TJ =125°C
1 µA
10 µA
Gate - Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -12 V, VDS = 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
I
D(ON)
g
GS(th)
DS(ON)
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.8 1.6 2 V
0.5 1.3 1.5
0.185 0.25
0.26 0.37
0.135 0.16
5 A
2.5 S
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
TJ =125°C
VGS = 4.5 V, ID = 1.1 A
TJ =125°C
VGS = 10 V, ID = 1.4 A
VGS = 4.5 V, VDS = 5 V
VDS = 5 V, ID = 1.1 A
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 80 pF
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 18 pF
140 pF
SWITCHING CHARACTERISTICS (Note 2)
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A,
Turn - On Rise Time 16 30 ns
VGS = 10 V, R
GEN
= 50 Ω
9 15 ns
Turn - Off Delay Time 26 50 ns
Turn - Off Fall Time 19 40 ns
Total Gate Charge VDS = 10 V, ID = 1.1 A,
Gate-Source Charge 1 nC
VGS = 5 V
2 3.5 nC
Gate-Drain Charge 2 nC
NDS351N Rev. E2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
design while R
P
D
Typical R
a. 250
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current 0.6 A
Maximum Pulsed Drain-Source Diode Forward Current 5 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.1 A (Note 2) 0.8 1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
is determined by the user's board design.
CA
θ
T
=
R
o
C/W when mounted on a 0.02 in2 pad of 2oz cpper.
T
J−TA
θJ A
JA
θ
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper.
J−TA
=
(t)
R
θ
J C
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
1a
2
= I
(t) × R
DS (ON ) T
D
+R
(t)
θ
CA
J
1b
is guaranteed by
JC
θ
NDS351N Rev. E2
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