Fairchild NDS351AN service manual
NDS351AN
NDS351AN
N-Channel, Logic Level, PowerTrench MOSFET
June 2003
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones,
PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are
needed in a very small outline surface mount package.
D
S
SuperSOT -3
TM
G
Features
• 1.4 A, 30 V. R
• Ultra-Low gate charge
• Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities
• High performance trench technology for extremely
low RDS(ON)
= 160 mΩ @ VGS = 10 V
DS(ON)
R
= 250 mΩ @ VGS = 4.5 V
DS(ON)
D
G
S
Absolute Maximum Ratings T
=25oC unless otherwise noted
A
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
STG
Drain-Source Voltage 30 V
Gate-Source Voltage
Drain Current – Continuous (Note 1a) 1.4 A
– Pulsed 10
Power Dissipation for Single Operation (Note 1a) 0.5
(Note 1b)
Operating and Storage Junction Temperature Range –55 to +150
± 20
0.46
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient (Note 1a) 250
Thermal Resistance, Junction-to-Case (Note 1) 75
°C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
351A NDS351AN 7’’ 8mm 3000 units
2003 Fairchild Semiconductor Corporation
NDS351AN Rev E(W)
V
W
°C
Electrical Characteristics T
GS
NDS351AN
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BVDSS
∆T
I
DSS
I
GSS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
J
VGS = 0 V, ID = 250 µA
ID = 250 µA,Referenced to 25°C
30 V
Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1
VDS = 24 V, VGS = 0 V, TJ = 55°C
Gate–Body Leakage
VGS = ±20 V, VDS = 0 V ±100
26
10
mV/°C
µA
µA
nA
On Characteristics (Note 2)
V
GS(th)
∆VGS(th)
∆T
R
DS(on)
I
D(on)
g
FS
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain–Source
On–Resistance
VDS = VGS, ID = 250 µA
ID = 250 µA,Referenced to 25°C
VGS = 10 V, ID = 1.4 A
VGS = 4.5 V, ID = 1.2 A
V
= 10 V, ID = 1.4 A, TJ = 125°C
0.8 2.1 3 V
–4
92
120
114
On–State Drain Current VGS = 4.5V, VDS = 5 V 3.5 A
Forward Transconductance VDS = 5 V, ID = 1.4 A 4 S
160
250
214
mV/°C
mΩ
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance 145 pF
Output Capacitance 35 pF
Reverse Transfer Capacitance
Gate Resistance
VDS = 15 V, V
GS
= 0 V,
f = 1.0 MHz
VGS = 15 mV, f = 1.0 MHz
15 pF
1.6
Ω
Switching Characteristics (Note 2)
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn–On Delay Time 3 6 ns
Turn–On Rise Time 8 16 ns
VDD = 15 V, ID = 1 A,
VGS = 10 V, R
GEN
= 6 Ω
Turn–Off Delay Time 16 29 ns
Turn–Off Fall Time
Total Gate Charge 1.3 1.8 nC
Gate–Source Charge 0.5 nC
VDS = 15 V, ID = 1.4 A,
VGS = 4.5 V
Gate–Drain Charge
2 4 ns
0.5 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
t
rr
Q
rr
Maximum Continuous Drain–Source Diode Forward Current 0.42 A
Drain–Source Diode Forward
VGS = 0 V, IS = 0.42 A (Note 2) 0.8 1.2 V
Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
IF = 1.4 A, diF/dt = 100 A/µs 11 nS
4 nC
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
is guaranteed by design while R
θJC
a) 250°C/W when mounted on a
2
0.02 in
pad of 2 oz. copper.
is determined by the user's board design.
θCA
b) 270°C/W when mounted on a
minimum pad.
NDS351AN Rev E(W)
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