Fairchild NDS332P service manual
June 1997
NDS332P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
-1 A, -20 V, R
R
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface Mount
package.
________________________________________________________________________________
= 0.41 Ω @ VGS= -2.7 V
DS(ON)
= 0.3 Ω @ V
DS(ON)
GS(th)
GS
< 1.0V.
= -4.5 V.
DS(ON)
.
D
G
S
Asolute Maximum Ratings T
Symbol Parameter NDS332P Units
V
DSS
V
GSS
I
D
P
D
TJ,T
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Drain-Source Voltage -20 V
Gate-Source Voltage - Continuous ±8 V
Drain Current - Continuous (Note 1a) -1 A
- Pulsed -10
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
= 25°C unless otherwise noted
A
0.46
© 1997 Fairchild Semiconductor Corporation
NDS332P Rev. E
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSS
I
GSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V
Zero Gate Voltage Drain Current
Gate - Body Leakage Current
Gate - Body Leakage Current
VDS = -16 V, V
GS
= 0 V
TJ = 55°C
VGS = 8 V, VDS= 0 V 100 nA
VGS = -8 V, VDS= 0 V -100 nA
-1 µA
-10 µA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -0.4 -0.6 -1 V
-0.3 -0.45 -0.8
0.35 0.41
0.5 0.74
Static Drain-Source On-Resistance
TJ =125°C
VGS = -2.7 V, ID = -1 A
TJ =125°C
Ω
VGS = -4.5 V, ID = -1.1 A 0.26 0.3
I
D(ON)
On-State Drain Current VGS = -2.7 V, VDS = -5 V -1.5 A
VGS = -4.5 V, VDS = -5 V -2.5
g
F
S
Forward Transconductance
VDS = -5 V, ID= -1 A
2.2
S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 105 pF
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 40 pF
195 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = -6 V, ID = -1 A,
Turn - On Rise Time 30 45 ns
VGS = -4.5 V, R
GEN
= 6 Ω
8 15 ns
Turn - Off Delay Time 25 45 ns
Turn - Off Fall Time 27 45 ns
Total Gate Charge VDS = -5 V, ID = -1 A,
Gate-Source Charge 0.5 nC
VGS = -4.5 V
3.7 5 nC
Gate-Drain Charge 0.9 nC
NDS332P Rev. E
Electrical Characteristics (T
TJ−
T
θJA
TJ−
T
θJC
θCA
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
Typical R
Maximum Continuous Source Current -0.42 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
A
(t)
=
(t)
R
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
A
2
=
+
R
R
(t)
= I
× R
DS(ON)@T
D
(t)
J
VGS = 0 V, IS = -0.42 A (Note 2)
-0.75 -1.2 V
is guaranteed by
JC
θ
1a 1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS332P Rev. E
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