Fairchild NDS331N service manual
NDS331N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
July 1996
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other battery powered circuits where fast
switching, and low in-line power loss are needed in a very
small outline surface mount package.
1.3 A, 20 V. R
R
= 0.21 Ω @ VGS= 2.7 V
DS(ON)
= 0.16 Ω @ VGS= 4.5 V.
DS(ON)
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOTTM-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDS331N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 20 V
Gate-Source Voltage - Continuous 8 V
Maximum Drain Current - Continuous (Note 1a) 1.3 A
- Pulsed 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b) 0.46
Operating and Storage Temperature Range -55 to 150 °C
STG
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient
(Note 1a)
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
250 °C/W
NDS331N Rev.E
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VDS = 16 V, VGS= 0 V
TJ =125°C
VGS = 8 V, VDS = 0 V
VGS = -8 V, VDS= 0 V
1 µA
10 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
0.5 0.7 1 V
TJ =125°C 0.3 0.53 0.8
R
DS(ON)
Static Drain-Source On-Resistance
VGS = 2.7 V, ID = 1.3 A
0.15 0.21
Ω
TJ =125°C 0.24 0.4
0.11 0.16
4
I
D(ON)
g
VGS = 4.5 V, ID = 1.5 A
On-State Drain Current VGS = 2.7 V, VDS = 5 V 3 A
VGS = 4.5 V, VDS = 5 V
FS
Forward Transconductance VDS = 5 V, I
= 1.3 A, 3.5 S
D
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 85 pF
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 28 pF
162 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 25 40 ns
VDD = 5 V, ID = 1 A,
VGS = 5 V, R
Gen
= 6 Ω
Turn - Off Delay Time 10 20 ns
Turn - Off Fall Time 5 20 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 0.3 nC
Gate-Drain Charge 1 nC
VDS = 5 V, ID = 1.3 A,
VGS = 4.5 V
5 20 ns
3.5 5 nC
NDS331N Rev.E
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
design while R
P
Typical R
a. 250
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current 0.42 A
Maximum Pulsed Drain-Source Diode Forward Current 10 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note 2) 0.8 1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
D
is determined by the user's board design.
CA
θ
−
T
J
(t)
=
R
θJ A
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
JA
θ
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
1a
−
T
T
T
A
(t)
o
A
2
J
=
C/W when mounted on a 0.02 in2 pad of 2oz copper.
= I
(t) × R
DS(ON ) T
R
θ
J C
D
+R
(t)
θ
CA
J
1b
is guaranteed by
JC
θ
NDS331N Rev.E
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