Fairchild NDS0605 service manual
July 2002
NDS0605
P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode field effect
transistors are produced using Fairchild’s proprietary,
high cell density, DMOS technology. This very high
density process has been designed to minimize onstate resistance, provide rugged and reliable
performance and fast switching. They can be used, with
a minimum of effort, in most applications requiring up to
180mA DC and can deliver current up to 1A.
This product is particularly suited to low voltage
applications requiring a low current high side switch.
Features
• −0.18A, −60V. R
• Voltage controlled p-channel small signal switch
• High density cell design for low R
= 5 Ω @ VGS = −10 V
DS(ON)
DS(ON)
• High saturation current
NDS0605
D
D
S
SG
SOT-23
Absolute Maximum Ratings T
G
o
=25
C unless otherwise noted
A
Symbol Parameter Ratings Units
V
Drain-Source Voltage
DSS
V
Gate-Source Voltage
GSS
ID Drain Current – Continuous (Note 1)
– Pulsed
D
TJ, T
TL
STG
Maximum Power Dissipation (Note 1) 0.36
Derate Above 25°C
Operating and Storage Junction Temperature Range
Maximum Lead Temperature for Soldering
Purposes, 1/16” from Case for 10 Seconds
−60
±20
−0.18
−1
2.9
−55 to +150 °C
300
Thermal Characteristics
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1) 350
V
V
A
W P
mW/°C
°C
°C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
65D NDS0605 7’’ 8mm 3000 units
2002 Fairchild Semiconductor Corpora tion
NDS0605 Rev B1(W)
NDS0605
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
∆BVDSS
∆T
J
I
Zero Gate Voltage Drain Current VDS = –48 V, VGS = 0 V –1
DSS
Breakdown Voltage Temperature
Coefficient
I
Gate–Body Leakage.
GSS
= 0 V, ID = –10 µA
V
GS
I
= –10 µA,Referenced to 25°C
D
= –48 V,VGS = 0 V TJ = 125°C
V
DS
= ±20 V, VDS = 0 V
V
GS
–60 V
–53
mV/°C
µA
–500
±100
µA
nA
On Characteristics (Note 2)
V
Gate Threshold Voltage VDS = VGS, ID = –250 µA –1 –1.7 –3 V
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
I
On–State Drain Current VGS = –10 V, VDS = – 10 V –0.6 A
D(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
= –250 µA,Referenced to 25°C
I
D
= –10 V, ID = –0.5 A
V
GS
= –4.5 V, ID = –0.25 A
V
GS
= –10 V,ID = –0.5 A,TJ=125°C
V
GS
3
1.0
1.3
1.7
5.0
7.5
10
mV/°C
Ω
gFS Forward Transconductance VDS = –10V, ID = – 0.2 A 0.07 0.43 S
Dynamic Characteristics
C
Input Capacitance 79 pF
iss
C
Output Capacitance 10 pF
oss
C
Reverse Transfer Capacitance
rss
RG Gate Resistance VGS = –15 mV, f = 1.0 MHz 10
V
= –25 V, V
DS
f = 1.0 MHz
= 0 V,
GS
4 pF
Ω
Switching Characteristics (Note 2)
t
Turn–On Delay Time 2.5 5 ns
d(on)
tr Turn–On Rise Time 6.3 12.6 ns
t
Turn–Off Delay Time 10 20 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 1.8 2.5 nC
Qgs Gate–Source Charge 0.3 nC
Qgd Gate–Drain Charge
= –25 V, ID = – 0.2 A,
V
DD
= –10 V, R
V
GS
= –48 V, ID = –0.5 A,
V
DS
= –10 V
V
GS
GEN
= 6 Ω
7.5 15 ns
0.4 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current
VSD Drain–Source Diode Forward
VGS = 0 V, IS = –0.5 A(Note 2) –0.8 –1.5 V
Voltage
trr Diode Reverse Recovery Time 17 nS
Qrr Diode Reverse Recovery Charge
Notes:
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
1. R
θJA
the drain pins. R
is guaranteed by design while R
θJC
a) 350°C/W when mounted on a
minimum pad..
θCA
I
= –0.5A
F
= 100 A/µs (Note 2)
d
iF/dt
is determined by the user's board design.
15 nC
–
0.18
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
NDS0610 Rev B1(W)
A
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