Fairchild NDH834P service manual
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NDH834P
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
May 1997
SuperSOTTM-8 P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
battery powered circuits or portable electronics where fast
switching, low in-line power loss, and resistance to transients
-5.6 A, -20 V. R
R
Proprietary SuperSOTTM-8 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
capability.
= 0.035 Ω @ VGS = -4.5 V
DS(ON)
= 0.045 Ω @ VGS = -2.7V.
DS(ON)
DS(ON)
.
are needed.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDH834P Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -20 V
Gate-Source Voltage ±8 V
Drain Current - Continuous (Note 1a) -5.6 A
- Pulsed -15
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 1.8 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1
0.9
THERMAL CHARACTERISTICS
R
qJA
R
qJC
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 70 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 20 °C/W
NDH834P Rev.C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V
Zero Gate Voltage Drain Current
VDS = -16 V, V
GS
= 0 V
-1 µA
TJ = 55oC -10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 8 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-0.4 -0.62 -1 V
TJ = 125oC -0.3 -0.4 -0.8
R
I
g
D(on)
FS
DS(ON)
Static Drain-Source On-Resistance
On-State Drain Current
Forward Transconductance
VGS = -4.5 V, ID = -5.6 A
TJ = 125oC
VGS = -2.7 V, ID = -5.2 A
VGS = -4.5 V, VDS = -5 V
VGS = -2.7 V, VDS = -5 V
VDS = - 5 V, ID = -5.6 A
0.029 0.035
0.039 0.063
0.038 0.045
-15 A
-5
18 S
Ω
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 745 pF
VDS = -15 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 270 pF
1820 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = -5 V, ID = -1 A,
V
= -4.5 V, R
Turn - On Rise Time 36 70 ns
GEN
GEN
= 6 Ω
15 30 ns
Turn - Off Delay Time 145 280 ns
Turn - Off Fall Time 85 160 ns
Total Gate Charge VDS = -10 V,
Gate-Source Charge 2.3 nC
ID = -5.6 A, VGS = -4.5 V
9.3 13 nC
Gate-Drain Charge 1.1 nC
NDH834P Rev.C
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
design while R
P
Typical R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current -1.5 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
(t)
D
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 70oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper.
c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper.
T
J−TA
=
(t)
R
θJA
θ
JC
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
+R
2
= I
(t) ×R
DS(ON ) T
D
(t)
θ
CA
J
1a
VGS = 0 V, IS = -1.5 A
1b
(Note 2)
1c
-0.7 -1.2 V
is guaranteed by
JC
θ
NDH834P Rev.C
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