Fairchild MM74HCT540, MM74HCT541 service manual
tm
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
June 2007
MM74HCT540, Inverting Octal 3-STATE Buffer
MM74HCT541, Octal 3-STATE Buffer
Features
■
TTL input compatible
Typical propagation delay: 12ns
■
■
3-STATE outputs for connection to system buses
■
Low quiescent current: 80µA
Output current: 6mA (Min.)
■
General Description
The MM74HCT540 and MM74HCT541 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed operation even when driving large
bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining
the low power consumption of CMOS. Both devices are
TTL input compatible and have a fanout of 15 LS-TTL
equivalent inputs.
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for
LS-TTL devices and can be used to reduce power consumption in existing designs.
The MM74HCT540 is an inverting buffer and the
MM74HCT541 is a non-inverting buffer. The 3-STATE
control gate operates as a two-input NOR such that if
either G1
high-impedance state.
In order to enhance PC board layout, the MM74HCT540
and MM74HCT541 offers a pinout having inputs and
outputs on opposite sides of the package. All inputs are
protected from damage due to static discharge by diodes
to V
or G2 are HIGH, all eight outputs are in the
and ground.
CC
Ordering Information
Package
Order Number
MM74HCT540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
MM74HCT541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
MM74HCT541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT540, MM74HCT541 Rev. 1.3
Number Package Description
Wide
Wide
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
Top View, MM74HCT540
Top View, MM74HCT541
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 2
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Rating
V
CC
V
IN
V
OUT
, I
I
IK
I
OUT
I
CC
T
STG
P
T
Note:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Supply Voltage –0.5 to +7.0V
DC Input Voltage –1.5 to V
DC Output Voltage –0.5 to V
Clamp Diode Current ±20mA
OK
DC Output Current, per pin ±35mA
DC V
or GND Current, per pin ±70mA
CC
Storage Temperature Range –65°C to +150°C
Power Dissipation
D
Note 2
S.O. Package only
Lead Temperature (Soldering 10 seconds) 260°C
L
+1.5V
CC
+0.5V
CC
600mW
500mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Min. Max. Units
V
CC
V
, V
IN
T
A
t
, t
r
Supply Voltage 4.5 5.5 V
DC Input or Output Voltage 0 V
OUT
CC
Operating Temperature Range –40 +85 °C
Input Rise and Fall Times 500 ns
f
V
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 3
=
=
=
=
=
DC Electrical Characteristics
V
5V ± 10% (unless otherwise specified)
CC
Symbol Parameter Conditions
V
V
V
V
I
I
OZ
I
CC
Minimum HIGH
IH
Level Input Voltage
Maximum LOW
IL
Level Input Voltage
Minimum HIGH
OH
Level Output
Voltage
Maximum LOW
OL
Level Voltage
Maximum Input
IN
Current
Maximum 3-STATE
Output Leakage
Current
Maximum
Quiescent Supply
Current
V
V
or V
IN
IH
|I
20µA V
OUT
6.0mA, V
|I
OUT
|I
7.2mA, V
OUT
V
V
IN
IH
20µA 0 0.1 0.1 0.1
|I
OUT
|I
6.0mA, V
OUT
|I
7.2mA, V
OUT
V
V
IN
CC
V
V
OUT
V
V
IN
CC
V
2.4V or 0.5V
IN
:
IL
or V
:
IL
or GND ±0.1 ±1.0 ±1.0 µA
or GND, G
CC
or GND, I
| =
| =
=
| =
=
=
| =
| =
=
| =
=
=
=
T
–40
T
25°C
A
A
to 85°C
2.0 2.0 2.0 V
0.8 0.8 0.8 V
V
CC
4.5V 4.2 3.98 3.84 3.7
CC
5.5V 5.2 4.98 4.84 4.7
CC
4.5V 0.2 0.26 0.33 0.4
CC
5.5V 0.2 0.26 0.33 0.4
CC
= V
IH
0µA 8.0 80 160 µA
OUT
(3)
0.6 1.0 1.3 1.5 mA
– 0.1 V
CC
±0.5 ±5.0 ±10 µA
– 0.1 V
CC
=
=
=
T
–55
A
to 125°C
– 0.1
CC
MM74HCT540, Inverting Octal 3-STATE Buffer MM74HCT541, Octal 3-STATE Buffer
UnitsTyp. Guaranteed Limits
V
V
Note:
3. Measured per input. All other inputs at V
or GND.
CC
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.3 4
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