Fairchild MM74HCT240, MM74HCT244 service manual
February 1984
Revised May 2005
MM74HCT240 • MM74HCT244
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-ST ATE Buffer
General Description
The MM74HCT240 and MM74HCT244 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed operation even w hen driving l arge bus
capacitances. These circuits achieve speeds comparable
to low power Schottky devices, while retaining the low
power consumption of CM OS. All three devices are TTL
input compatible and have a fanou t of 15 LS-TTL equivalent inputs.
MM74HCT devices are in tended to interfa ce between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumpti on in
existing designs.
The MM74HCT240 is an inverting buffer and the
MM74HCT244 is a non-invertin g buffer. Each device has
two active low enables (1G and 2G), and each enable independently controls 4 buffers.
All inputs are protected from damage due to static discharge by diodes to V
and Ground.
CC
Features
■ TTL input compatible
■ Typical propagation delay: 14 ns
■ 3-STATE outputs for connection to system buses
■ Low quiescent current: 80
■ High output drive current: 6 mA (min)
P
A
Ordering Code:
Order Numbe r Package Numb er Package Description
MM74HCT240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HCT244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also availab l e in Tape and Reel. Specify by appending the suffix let t er “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT240
© 2005 Fairchild Semiconductor Corporation DS005365 www.fairchildsemi.com
Top View
MM74HCT244
Truth Tables
MM74HCT240
1G
1A 1Y 2G 2A 2Y
LLHLLH
LHLLHL
HLZHLZ
HHZHHZ
H HIGH Level L LOW Level Z High Impedance
MM74HCT240 • MM74HCT244
Logic Diagrams
MM74HCT240 MM74HCT244
MM74HCT244
1G 1A 1Y 2G 2A 2Y
LLLLLL
LHHLHH
HLZHLZ
HHZHHZ
www.fairchildsemi.com 2
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
)
IN
)
OUT
, IOK)
IK
DC Output Current, per pin (I
DC V
or GND Current, per pin (ICC)
CC
Storage Temperature Range (T
Power Dissipation (P
)
D
OUT
STG
)
)
1.5 to V
0.5 to V
65q
0.5 to 7.0V
C to 150qC
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260
DC Electrical Characteristics
V
5V r10% (unless otherwise specified)
CC
Symbol Parameter Conditions
V
V
V
V
I
IN
I
OZ
I
CC
Minimum HIGH Level 2.0 2.0 2.0 V
IH
Input Voltage
Maximum LOW Level 0.8 0.8 0.8 V
IL
Input Voltage
Minimum HIGH Level V
OH
Output Voltage |I
Maximum LOW Level V
OL
Voltage |I
Maximum Input V
Current VIH or V
Maximum 3-STATE V
Output Leakage G
Current G V
Maximum Quiescent V
Supply Current I
Note 4: Measured per input. All other inputs at VCC or GND.
VIH or V
IN-EE
| 20 PAV
OUT
| 6.0 mA, V
|I
OUT
|I
| 7.2 mA, V
OUT
VIH or V
|I
|I
OUT
V
IN
OUT
OUT
OUT
IN
OUT
V
IN
IN
IL
| 20 PA 0 0.1 0.1 0.1 V
| 6.0 mA, V
| 7.2 mA, V
VCC or GND,
IL
VCC or GND
IH
IL
VCC or GND 4.0 40 160
0 PA
2.4V or 0.5V (Note 4) 0.6 1.0 1.3 1.5 mA
Recommended Operating
Conditions
1.5V
CC
CC
r
r
r
IL
CC
CC
CC
CC
20 mA
35 mA
70 mA
Supply Voltage (V
0.5V
DC Input or Output Voltage 0 V
, V
(V
IN
OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf) 500 ns
(t
r
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwis e s pecified all voltages are referenced to ground.
Note 3: Power Dissipation tem perature d erating — plastic “N” package:
12 mW/qC from 65qC to 85qC.
q
C
TA
25qCTA
Typ Guaranteed Limits
4.5V 4.2 3.98 3.84 3.7 V
5.5V 5.2 4.98 4.84 4.7 V
4.5V 0.2 0.26 0.33 0.4 V
5.5V 0.2 0.26 0.33 0.4 V
CCVCC
)4.55.5V
CC
)
40 to 85qCTA 55q
0.1 VCC
r
0.05
r
0.25
0.1 VCC
r
0.5
r
2.5
Min Max Units
)4085qC
A
to 125qC
0.1 V
r
1.0
r
10
CC
MM74HCT240 • MM74HCT244
V
Units
P
A
P
A
P
A
3 www.fairchildsemi.com
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