Fairchild MM74HC74A service manual
MM74HC74A
Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
September 1983
Revised January 2005
General Description
The MM74HC74A utilizes advanced silicon-gate CMOS
technology to achieve operating speeds similar to the
equivalent LS-TTL par t. It possesse s the hig h noise imm unity and low power consumpt ion of standard CMOS integrated circuits, along with the ability to drive 1 0 LS-TTL
loads.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q
data input is tra nsferred to the outp ut during the posi tivegoing transition of the clock pulse. Preset and clear are
independent of the clock a nd accomplish ed by a low level
at the appropriate input.
outputs. The logic level present at the
The 74HC logic family is functionally and pinout compatible
with the standard 74LS logic family. All inputs are protected
from damage due to static discharge by internal diode
clamps to V
and ground.
CC
Features
■ Typical propagation delay: 20 ns
■ Wide power supply range: 2–6V
■ Low quiescent current: 40
■ Low input current: 1
■ Fanout of 10 LS-TTL loads
µA maximum (74HC Series)
µA maximum
Ordering Code:
Order Number
MM74HC74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC74AMX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC74ASJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC74AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
MM74HC74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Pb-Free pac k age per JEDEC J-STD- 020B.
Connection Diagram
Package
Number
Package Description
Wide
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
PR CLR CLK D Q Q
Note: Q0 = the level of Q before the indicated input conditions were estab-
lished.
Note 1: This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) level.
© 2005 Fairchild Semiconductor Corporation DS005106 www.fairchildsemi.com
Inputs Outputs
LHXX H L
HL XX L H
L L X X H (Note 1) H (Note 1)
HH
HH
HH LX Q0 Q
↑ HH L
↑ LL H
0
Logic Diagram
MM74HC74A
www.fairchildsemi.com 2
Absolute Maximum Ratings(Note 2)
(Note 3)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
DC V
or GND Current, per pin
CC
(I
) ±50 mA
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 4) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds) 260
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±25 mA
OUT
) −65°C to +150°C
STG
)
D
)
L
CC
CC
Recommended Operating
Conditions
+1.5V
Supply Voltage (V
+0.5V
DC Input or Output Voltage 0 V
(V
IN, OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf) V
(t
r
CC
V
CC
V
CC
Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 3: Unless otherwise specified all voltages are referenced to ground.
Note 4: Power Dissipation te mperature d erating — pl astic “N” package: −
°C
12 mW/°C from 65°C to 85°C.
)26V
CC
)
) −40 +85 °C
A
= 2.0V 1000 ns
= 4.5V 500 ns
= 6.0V 400 ns
Min Max Units
CC
DC Electrical Characteristics (Note 5)
Symbol Parameter Conditions
V
V
V
V
I
I
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
Minimum HIGH Level V
OH
Output Voltage |I
Maximum LOW Level V
OL
Output Voltage |I
Maximum Input V
IN
Current
Maximum Quiescent V
CC
Supply Current I
Note 5: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
rent (I
IN
= VIH or V
IN
OUT
VIN = VIH or V
|I
OUT
|I
OUT
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
I N =VCC
OUT
and VIL occur at V
IH
IL
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
IL
| ≤ 4.0 mA 4.5V 4.3 3.98 3.84 3.7 V
| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V
= VIH or V
IL
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
= VIH or V
IL
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
or GND 6.0V 4.0 40 80 µA
= 0 µA
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
MM74HC74A
V
Units
3 www.fairchildsemi.com
Loading...