Fairchild MM74HC574 service manual

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MM74HC574
3-STATE Octal D-Type Edge-Triggered Flip-Flop

MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop

September 1983
Revised May 2005

General Description

The MM74HC574 high speed octal D-type flip-flops utilize
advanced silicon-gate P-well CMOS technology. They pos­sess the high noise immun ity and low pow er consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are id e­ally suited for interfacing with bus lines in a bus organ ized
system.

These devices are posi tive edge triggered flip-flops. Data
at the D inputs, meeting the set-up and hold time require­ments, are transferred to th e Q outputs on positive going
transitions of the CL OCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high im pedance state, regard less of what
signals are present at th e other inpu ts and the state of the
storage elements.

The 74HC logic famil y is speed , functio n, and pin out com­patible with the standard 74LS logic fa mily. All inputs are
protected from dama ge due to static discharge by i nternal
diode clamps to V

and ground.

CC

Features

■ Typical propagation delay: 18 ns

■ Wide ope rat i ng voltage range: 2V–6V

■ Low input current: 1

■ Low quiescent current: 80

■ Compatible with bus-oriented systems

■ Output drive capability: 15 LS-TTL loads

P

A maximum

P

A maximum

Ordering Code:

Order Number Package Number Package Description

MM74HC574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also availab l e in Tape and Reel. Specify by appending the suffix let t er “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Top View

© 2005 Fairchild Semiconductor Corporation DS005213 www.fairchildsemi.com

Truth Table

Output Clock Data Output

Control

n
n

HH
LL

0

L
L
LLXQ

H HIGH Level

LOW Level

L
X

Don't Care

n

Transition from LOW-to- H IG H
High Impedance State

Z
Q

The level of the output before steady state in put conditions were

0

established

HXXZ

Absolute Maximum Ratings(Note 1)

(Note 2)

Supply Voltage (VCC)
DC Input Voltage (V
DC Output Voltage (V

MM74HC574

Clamp Diode Current (I
DC Output Current, per pin (I
DC V

or GND Current, per pin (ICC)

CC

Storage Temperature Range (T
Power Dissipation (P

)

IN

)

OUT

, IOK)

IK

OUT

STG

)

D

(Note 3) 600 mW
S.O. Package only 500 mW

Lead Temperature (T

)

L

(Soldering 10 seconds) 260



1.5 to V



0.5 to V

)

)

65q



0.5 to 7.0V

CC
CC

r

20 mA

r

35 mA

r

70 mA

C to 150qC

Recommended Operating
Conditions



1.5V

Supply Voltage (V



0.5V

DC Input or Output Voltage 0 V

(V

IN,VOUT

Operating Temperature Range (T
Input Rise or Fall Times

, tf) V

(t

r

Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.

Note 2: Unless otherwise specifie d all voltages are referenced to ground.

q

C

Note 3: Power Dissipation temp erature de rating — plastic “N” package:
12 mW/qC from 65qC to 85qC.

)26V

CC

)

)4085

A

2.0V 1000 ns

CC

V

4.5V 500 ns

CC

V

6.0V 400 ns

CC

Min Max Units

CC

DC Electrical Characteristics (Note 4)

TA

Symbol Parameter Conditions

V

Minimum HIGH Level Input 2.0V 1.5 1.5 1.5

IH

V

Maximum LOW Level Input 2.0V 0.5 0.5 0.5

IL

V

Minimum HIGH Level Output V

OH

Voltage |I

V

Maximum LOW Level Output V

OL

Voltage |I

I

Maximum Input Current V

IN

I

Maximum 3-STATE V

OZ

Output Leakage Current OC V

I

Maximum Quiescent Supply V

CC

Current I

'

I

Quiescent Supply Current VCC 5.5V OE 1.0 1.5 1.8 2.0

CC

Note 4: For a power supply of 5V r10% the worst-case output voltages (VOH, and VOL) occur for HC a t 4.5V. Thus the 4.5V values s hould be used wh en
designing with this supply. Worst-case V

, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6.0V values should be used.

rent (I

IN

VIH or V

IN

OUT

V

IN

|I

OUT

|I

OUT

IN

OUT

V

IN

|I

OUT

|I

OUT

IN
OUT

IN

OUT

or 0.4V (Note 4) DATA 0.4 0.5 0.6 0.7

and VIL occur at V

IH

IL

| d 20 PA 2.0V 2.0 1.9 1.9 1.9

VIH or V

IL

| d 6.0 mA 4.5V 4.2 3.98 3.84 3.7
| d 7.8 mA 6.0V 5.7 5.48 5.34 5.2
VIH or V

IL

| d 20 PA 2.0V 0 0.1 0.1 0.1

VIH or V

IL

| d 6.0 mA 4.5V 0.2 0.26 0.33 0.4
| d 7.8 mA 6.0V 0.2 0.26 0.33 0.4
VCC or GND 6.0V

VCC or GND

IH

VCC or GND

0 PA 6.0V 8.0 80 160

CC

V

CC

6.0V 4.2 4.2 4.2

6.0V 1.8 1.8 1.8

6.0V 6.0 5.9 5.9 5.9

6.0V 0 0.1 0.1 0.1

6.0V

5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage cur-

25qCTA 

Typ Guaranteed Limits

r

0.1

r

0.5

40 to 85qCTA 

r

1.0

r

5.0

55 to 125qC

r

1.0

r

10

V

q

C

Units

P

P

P

mAper Input Pin VIN 2.4V CLK 0.6 0.8 1.0 1.1



VVoltage 4.5V 3.15 3.15 3.15

VVoltage 4.5V 1.35 1.35 1.35

V4.5V 4.5 4.4 4.4 4.4

V

V4.5V 0 0.1 0.1 0.1

V

A

A

A

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AC Electrical Characteristics

V

5V, TA 25qC, t

CC

t

6 ns

r

f

Symbol Parameter Conditions Typ

f
t
t

t

t
t
t

MAX
PHL
PZH

PHZ

S
H
W

, t
, t

, t

Maximum Operating Frequency 60 33 MHz
Maximum Propagation Delay, Clock to Q CL

PLH

Maximum Output Enable Time RL

PZL

Maximum Output Disable Time RL

PLZ

45 pF 17 27 ns
1 k

:

C

45 pF

L

1 k

:

CL

5 pF
Minimum Setup Time, Data to Clock 10 12 ns
Minimum Hold Time, Clock to Data
Minimum Pulse Clock Width 8 15 ns

AC Electrical Characteristics

V

2.0  6.0V, C

CC

Symbol Parameter Conditions

f

t

MAX

PHL

Maximum Operating Frequency CL

, t

Maximum Propagation CL

PLH

Delay, Clock to Q CL

, t

t

PZH

Maximum Output Enable RL

PZL

Time CL

t

, t

PHZ

t

S

t

H

t

THL

t

W

tr,t

C

PD

Maximum Output Disable Time RL

PLZ

Minimum Setup Time 2.0V 6 12 15 18

Minimum Hold Time 2.0V

, t

Maximum Output Rise CL

TLH

Minimum Clock Pulse Width 2.0V 30 15 20 24

Maximum Clock Input Rise 2.0V 1000 1000 1000

f

Power Dissipation Capacitance OC V
(Note 5) (per latch) OC GND 58

C

IN

Maximum Input Capacitance 5 10 10 10 pF

L

50 pF, t

t

6 ns (unless otherwise specified)

r

f

50 pF 2.0V 33 28 23

50 pF 2.0V 18 30 38 45
150 pF 2.0V 51 155 194 233

C

50 pF 4.5V 13 23 29 35

L

150 pF 4.5V 19 31 47 47

C

L

CL

50 pF 6.0V 12 20 25 30

C

150 pF 6.0V 18 27 34 41

L

1 k

:

50 pF 2.0V 22 30 38 45

C

150 pF 2.0V 59 180 225 270

L

50 pF 4.5V 14 28 35 42

C

L

CL

150 pF 4.5V 20 36 45 54

C

50 pF 6.0V 12 24 30 36

L

150 pF 6.0V 18 31 39 47

C

L

1 k

:

50 pF 4.5V 12 25 31 38

L

50 pF 2.0V 6 12 15 18

CC

TA

V

CC

25qCTA 

Typ Guaranteed Limits

6.0V 35 28 23

2.0V 15 30 38 45

6.0V 10 21 27 32

6.0V 17 21 25



15 6 8

6.0V 0 0 0

6.0V 6 10 13 15

6.0V 8 14 18 20

6.0V 400 400 400
5

Guaranteed

Limit

Units

19 28 ns

14 25 ns



35ns

40 to 85qCTA 

55 to 125qC

Units

MHz4.5V 30 24 20

ns

ns

ns

ns

ns

ns

nsC

nsData to Clock 4.5V 20 25 30

nsClock to Data 4.5V 0 0 0

nsand Fall Time 4.5V 7 12 15 18

ns4.5V 9 16 20 24

nsand Fall Time 4.5V 500 500 500

pF

MM74HC574

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