The MM74HC4046 is a low power phase lock loop utilizing
advanced silicon-gate CMOS technology to obtain high frequency operation bot h in the phase comparator and V CO
sections. This device contai ns a low power linear voltage
controlled oscillator (VCO), a source follower, and three
phase comparators. The thre e phase comparators ha ve a
common signal input and a common comparator input. The
signal input has a self biasing ampl ifier allowing sign als to
be either capacitively co upled to the phase comparators
with a small signal or direc tly coupled with standar d input
logic levels. This device is similar to the C D4046 except
that the Zener diode of the metal gate C MOS device has
been replaced with a third phase comparator.
Phase Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that ma intains a 90 phase shift
between the VCO’s center freque ncy and the input signal
(50% duty cycle input waveforms). This phase detec tor is
more susceptible to locking onto harmonics of the input frequency than phase compara tor I, but provi des bet ter noise
rejection.
Phase comparator III is an S R fl ip -fl op ga te. It can b e us ed
to provide the phase co mparator functions an d i s s imi lar to
the first comparator in performance.
Phase comparator II is an edge se nsitive digit al seque ntial
network. Two signal outputs are provided, a comparator
output and a phase pulse output. The comparator output is
a 3-STA T E output that provides a signal that locks the VCO
output signal to the i n pu t sign al w ith 0 ph ase shift between
them. This comparator is more susceptible to noise throwing the loop out of lock, but is less likely to lock onto h armonics than the other t wo comparators.
In a typical applicat ion any one of the three compara tors
feed an external fil t er net w ork w hich i n tur n f eed s th e VCO
input. This input is a very high impedance CMOS input
which also drives the source follower. The VCO’s operating
frequency is set by three external components co nnected
to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided
to disable the VCO and the source follower, providing a
method of putting the IC in a low power state.
The source follower is a MOS transistor whose gate is connected to the VCO input and whose drain connects the
Demodulator outp ut. This out put normally is used by tying
a resistor from pin 10 to ground , and p rovides a means of
looking at the VCO input without loading down modifying
the characteristics of the PLL filter.
Features
■ Low dynamic power consumption : (V
■ Maximum VCO operating freque ncy:
12 MHz (V
■ Fast comparator response time (V
Comparator I: 25 ns
Comparator II: 30 ns
Comparator III: 25 ns
■ VCO has high linearity and high temperature stability
CC
= 4.5V)
CC
CC
= 4.5V)
= 4.5V)
Ordering Code:
Order NumberPackage NumberPackage Description
MM74HC4046MM16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC4046SJM16D16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4046MTCMTC1616-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4046NN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Supply Voltage (VCC)−0.5 to + 7.0V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current per pin (I
DC V
or GND Current, per pin (ICC)±50 mA
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3)600 mW
S.O. Package only500 mW
Lead Temperature (T
(Soldering 10 seconds)260
)−1.5 to VCC +1.5V
IN
)−0.5 to VCC + 0.5V
OUT
, IOK)±20 mA
IK
)±25 mA
OUT
)−65°C +150°C
STG
)
D
)
L
Recommended Operating
Conditions
MinMax Units
Supply Voltage (V
DC Input or Output Voltage
, V
(V
IN
OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf) V
(t
r
CC
V
CC
V
Note 1: Maximum Ratings are those v alues beyo nd which damage to t he
device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
°C
Note 3: Power Dissipation te mperature d erating — pl astic “N” package: −
12 mW/°C from 65°C to 85°C.
CC
)26V
CC
)0V
) −40+85°C
A
= 2.0V1000ns
= 4.5V500ns
= 6.0V400ns
CC
DC Electrical Characteristics (Note 4)
SymbolParameterConditions
V
Minimum HIGH Level 2.0V1.51.51.5V
IH
Input Voltage4.5V3.153.153.15V
V
Maximum LOW Level 2.0V0.50.50.5V
IL
Input Voltage 4.5V1.351.351.35V
V
Minimum HIGH Level V
OH
Output Voltage|I
V
Maximum Low Level V
OL
Output Voltage|I
I
Maximum Input Current (Pins 3,5,9) V
IN
I
Maximum Input Current (Pin 14)V
IN
I
Maximum 3-STATE OutputV
OZ
Leakage Current (Pin 13)
I
Maximum Quiescent V
CC
Supply CurrentI
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
rent (I
IN
and VIL occur at V
IH
= VIH or V
IN
| ≤ 20 µA2.0V2.01.91.91.9V
OUT
V
= VIH or V
IN
|I
| ≤ 4.0 mA4.5V4.23.983.843.7V
OUT
| ≤ 5.2 mA6.0V5.75.485.345.2V
|I
OUT
= VIHor V
IN
| ≤ 20 µA2.0V00.10.10.1V
OUT
V
= VIH or V
IN
|I
| ≤ 4.0 mA4.5V0.20.260.330.4V
OUT
|I
| ≤ 5.2 mA6.0V0.20.260.330.4V
OUT
= VCCor GND6.0V±0.1±1.0±1.0µA
IN
= V
or GND6.0V205080100µA
IN
CC
= VCC or GND 6.0V±0.5±5.0±10µA
OUT
= VCC or GND6.0V3080130160µA
IN
= 0 µA
OUT
VIN = VCC or GND6.0V600150024003000µA
Pin 14 Open
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
CC
V
CC
6.0V4.24.24.2V
6.0V1.81.81.8V
IL
4.5V4.54.44.44.4V
6.0V6.05.95.95.9V
IL
IL
4.5V00.10.10.1V
6.0V00.10.10.1V
IL
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
TypGuaranteed Limits
MM74HC4046
V
Units
3www.fairchildsemi.com
AC Electrical Characteristics V
SymbolParametersConditions
AC CoupledC (series) = 100 pF2.0V25100150200mV
MM74HC4046
Signal In6.0V135250300350mV
tr, t
Maximum Output2.0V307595110ns
f
Rise and Fall Time4.5V9151922ns
Input Sensitivity,f
C
Maximum Input Capacitance7pF
IN
Phase Comparator I
t
, t
Maximum 2.0V65200250300ns
PHL
PLH
Propagation Delay4.5V25405060ns
Phase Comparator II
Maximum 3-STATE2.0V75225280340ns
t
PZL
Enable Time4.5V25455668ns
t
, t
Maximum 3-STATE2.0V88240300360ns
PZH
PHZ
Enable Time4.5V30486072ns
t
Maximum 3-STATE2.0V90240300360ns
PLZ
Disable Time4.5V32486072ns
t
, t
Maximum 2.0V100250310380ns
PHL
PLH
Propagation Delay4.5V34506375ns
HIGH-to-LOW to Phase Pulses6.0V27435364ns