MM74C906 • MM74C907
Hex Open Drain N-Channel Buffers •
Hex Open Drain P-Channel Buffers
MM74C906 • MM74C907 Hex Open Drain N-Channel Buffers • Hex Open Drain P-Channel Buffer s
October 1987
Revised January 1999
General Description
The MM74C906 and MM74C907 buffers employ monolithic
CMOS technology in achieving open drain outputs. The
MM74C906 consists of six inverters driving six N -channel
devices; and the MM74C907 consists of six inverters dr iving six P-channel devices. The open drain feature of these
buffers makes level shifting or wire AND and wire OR functions by just the addition of pull-up or pull-down re sistors.
All inputs are protected from static discharge by diode
clamps to V
and to ground.
CC
Features
■ Wide supply voltage range: 3V to 15V
■ Guaranteed noise margin: 1V
■ High noise immunity: 0.45 V
■ High current sourcing and sinking open drain outputs
Voltage at Any Input Pin−0.3V to VCC +0.3V
Voltage at Any Output Pin
Operating Temperature Range
MM74C906/MM74C907 −40°C to +85°C
Storage Temperature Range−65°C to +150°C
Power Dissipation
Dual-In-Line 700 mW
Operating V
Absolute Maximum V
Lead Temperature (T
(Soldering, 10 seconds)260°C
Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the
safety of the device cannot be guaranteed. Ex ce pt for “O perating Temperature Range” they are not mean t to imply that the devices sho uld be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device op eration.
Range3V to 15V
CC
CC
)
L
Small Outline500 mW
MM74C906 • MM74C907
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: “C” used in calcu lating propagation inc ludes output load capacity (C
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C
AN-90. (Assumes ou t puts are open).
= 50 pF, unless otherwise specified
L
Propagation Delay Time
to a Logical “0”
MM74C906VCC = 5.0V, R = 10k150ns
MM74C907VCC = 5.0V (Note 3)150 + 0.7 RCns
Propagation Delay Time
to a Logical “1”
MM74C906VCC = 5.0V (Note 3)150 + 0.7 RCns
MM74C907VCC = 5.0V, R = 10k150ns
Input Capacitance(Note 4)5.0pF
Output Capacity(Note 4)20pF
Power Dissipation Capacity(Note 5) Per Buffer30pF
determines th e no load AC power con sumption of any CMOS device. For comp lete explanatio n see Family Characte ristics App lication No te,
PD
VCC =10V, R = 10k75ns
VCC = 10V (Note 3)75 + 0.7 RCns
VCC = 10V (Note 3)75 + 0.7 RCns
VCC = 10V, R = 10k75ns
) plus device output capacity (C
L
OUT
).
Typical Applications
Wire OR Gate
Wire AND Gate
MM74C906 • MM74C907
Note: Can be extended to more t han 2 inputs.
CMOS or TTL to PMOS Interface
Note: VCC + VDD ≤ 18V
≤ 15V
V
CC
Note: Can be extended to more than 2 inputs.
CMOS or TTL to CMOS at a Higher V
CC
3www.fairchildsemi.com
Physical Dimensions in ches (millimeters) unless otherwise noted
MM74C906 • MM74C907
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
Package Number N14A
2. A critical comp onent in any com ponent of a l ife support
device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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