Fairchild MM74C86 service manual
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MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
October 1987
Revised January 1999
General Description
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operatin g range,
low power consumption and high noise margin these gates
provide basic functions used in the imp lementation of digital integrated circuit systems. The N- and P-channel
enhancement mode transisto rs provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage
current is consumed during static condition. Al l inputs are
protected from dam age due to static discharge by diode
clamps to V
and GND.
CC
Features
■ Wide supply voltage range: 3.0V to 15V
■ Guaranteed noise margin: 1.0V
■ High noise immunity: 0.45 V
■ Low power: TTL compatibility:
Fan out of 2 driving 74L
■ Low power consumption: 10 nW/package (typ.)
■ The MM74C86 follows the MM74 LS86 Pinout
CC
(typ.)
Ordering Code:
Order Number Package Number Package Description
MM74C86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering co de.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
ABY
LLL
LHH
HLH
HHL
H = HIGH Level
L = LOW Level
Inputs Output
Top View
© 1999 Fairchild Semiconductor Corporation DS005887.prf www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Voltage at any Pin (Note 1) −0.3V to VCC + 0.3V
Operating Temperature Range −40°C to +85°C
MM74C86
Storage Temperature Range −65°C to +150°C
Power Dissipa tion (P
Dual-In-Line Package 700 mW
Small Outline 500 mW
Operating Range (V
)
D
) 3.0V to 15V
CC
Absolute Maximum (V
Lead Temperature
(Soldering, 10 seconds) 260°C
Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the
safety of the device cannot be guaranteed. Ex ce pt for “O perating Temperature Range” they are not mean t to imply that the devices sho uld be operated at these limits. The Electrical Ch arac t eristics table provides co nditions
for actual device operation.
)18V
CC
DC Electrical Characteristics
Min/max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
CMOS/LPTTL INTERFA CE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Logical “1” Input Voltage VCC = 5.0V 3.5 V
VCC = 10V 8.0 V
Logical “0” Input Voltage VCC = 5.0V 1.5 V
VCC = 10V 2.0 V
Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA4.5 V
VCC = 10V, IO = −10 µA9.0 V
Logical “0” Output Voltage VCC = 5.0V, IO = +10 µA0.5V
VCC = 10V, IO = +10 µA1.0V
Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA
Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA
Supply Current VCC = 15V 0.01 15 µA
Logical “1” Input Voltage VCC = 4.75V VCC−1.5 V
Logical “0” Input Voltage VCC = 4.75V 0.8 V
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V
Output Source Current VCC = 5.0V, V
= 0V −1.75 −3.3 mA
OUT
(P-Channel) TA = 25°C
Output Source Current VCC = 10V, V
= 0V −8.0 −15 mA
OUT
(P-Channel) TA = 25°C
Output Sink Current VCC = 5.0V, V
OUT
= V
CC
1.75 3.6 mA
(N-Channel) TA = 25°C
Output Sink Current VCC = 10V, V
OUT
= V
CC
8.0 16 mA
(N-Channel) TA = 25°C
AC Electrical Charac teristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
t
pd
C
IN
C
PD
Note 2: AC Parameters are guara nt eed by DC correlated test ing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C
AN-90.
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Propagation Time to Logical VCC = 5.0V 110 185 ns
“1” or “0” VCC = 10V 50 90 ns
Input Capacitance (Note 3) 5.0 pF
Power Dissipation Capacitance Per Gate (Note 4) 20 pF
determines t he no loa d AC power c ons um ption of a ny CM OS d evice. For com plet e expla natio n se e Family Cha ract eris tics Appl icat ion N ote —
PD
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