Fairchild MM74C73, MM74C76 service manual
查询MM74C76供应商
MM74C73 • MM74C76
Dual J-K Flip-Flops with Clear and Preset
MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset
October 1987
Revised May 2002
General Description
The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementa ry M OS (CMOS) integrated ci rcu its co nstructed with N- and P-channel enhancemen t transistors.
Each flip-flop has indepen dent J, K, clo ck and clear inp uts
and Q and Q outputs. The MM74C76 flip flops also include
preset inputs and a re supplied in 16 pin packages. T his
flip-flop is edge sen sitive to the clock input and change
state on the negative going transition of the clock pulse.
Clear or preset is indepe ndent of the clock and is accomplished by a low level on the respective input.
Features
■ Supply voltage range: 3V to 15V
■ Tenth power TTL compatible: Drive 2 LPTTL loads
■ High noise immunity: 0.45 V
■ Low power: 50 nW (typ.)
■ Medium speed operation: 10 MHz (typ.)
CC
(typ.)
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Order Number Package Number Package Description
MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C76M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74C76N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
MM74C73
MM74C76
Note: A logic “0” on clear sets Q to a logic “0”.
Note: A logic “0” on clear sets Q to logic “0”.
Top View
© 2002 Fairchild Semiconductor Corporation DS005884 www.fairchildsemi.com
Note: A logic “0” on preset sets Q to a logic “1”.
Top View
Truth Table
JKQ 0000
00Q
0 1 0 10 01
MM74C73 • MM74C76
tn = bit time before clock pulse
t
n+1
101 11Q
11Q
= bit time after clock pulse
Logic Diagrams
t
n
t
n+1
n
n
Preset Clear
01 10
Note 1: No change in output from previous state
Q
n
n
(Note 1) (Note 1)
Q
n
Q
n
MM74C73
MM74C76
Transmission Gate
www.fairchildsemi.com 2
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range
Storage Temperature
−55°C to +125°C
−65°C to +150°C
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature
(Soldering, 10 seconds) 260
Operating V
(Max) 18V
V
CC
Range +3V to 15V
CC
Note 2: “Absolute Maximum Ratings” are those values bey ond which the
safety of the device cannot be guaranteed. Except for “Operating T emperature Range” they are not meant to imply that the devic es should be oper-
°C
ated at these limits. The table of Electrical Characteristics provides
conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
LOW POWER TTL TO CMOS INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Logical “1” Input Voltage VCC = 5V 3.5
VCC = 10V 8
Logical “0” Input Voltage VCC = 5V 1.5
V
= 10V 2
CC
Logical “1” Output Voltage VCC = 5V 4.5
VCC = 10V 9
Logical “0” Output Voltage VCC = 5V 0.5
= 10V 1
V
CC
Logical “1” Input Current VCC = 15V 1 µA
Logical “0” Input Current VCC = 15V −1 µA
Supply Current VCC = 15V 0.050 60 µA
Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V
Logical “0” Input Voltage VCC = 4.75V 0.8 V
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V
Output Source Current VCC = 5V, V
TA = 25°C, V
Output Source Current VCC = 10V, V
TA = 25°C, V
Output Sink Current VCC = 5V, V
TA = 25°C, V
Output Sink Current VCC = 10V, V
TA = 25°C, V
IN(0)
OUT
OUT
IN(1)
OUT
OUT
IN(0)
IN(1)
= 0V
= 0V
= 0V
= 0V
= 5V
= V
= 10V
= V
−1.75 mA
−8mA
CC
CC
1.75 mA
8mA
MM74C73 • MM74C76
V
V
V
V
3 www.fairchildsemi.com
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