Fairchild MM74C73, MM74C76 service manual

查询MM74C76供应商

MM74C73 • MM74C76
Dual J-K Flip-Flops with Clear and Preset

MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset

October 1987
Revised May 2002

General Description

The MM74C73 and MM74C76 dual J-K flip-flops are mono­lithic complementa ry M OS (CMOS) integrated ci rcu its co n­structed with N- and P-channel enhancemen t transistors.
Each flip-flop has indepen dent J, K, clo ck and clear inp uts
and Q and Q outputs. The MM74C76 flip flops also include
preset inputs and a re supplied in 16 pin packages. T his
flip-flop is edge sen sitive to the clock input and change
state on the negative going transition of the clock pulse.
Clear or preset is indepe ndent of the clock and is accom­plished by a low level on the respective input.

Features

■ Supply voltage range: 3V to 15V

■ Tenth power TTL compatible: Drive 2 LPTTL loads

■ High noise immunity: 0.45 V

■ Low power: 50 nW (typ.)

■ Medium speed operation: 10 MHz (typ.)

CC

(typ.)

Applications

• Automotive

• Data terminals

• Instrumentation

• Medical electronics

• Alarm systems

• Industrial electronics

• Remote metering

• Computers

Ordering Code:

Order Number Package Number Package Description

MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C76M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74C76N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

MM74C73

MM74C76

Note: A logic “0” on clear sets Q to a logic “0”.

Note: A logic “0” on clear sets Q to logic “0”.

Top View

© 2002 Fairchild Semiconductor Corporation DS005884 www.fairchildsemi.com

Note: A logic “0” on preset sets Q to a logic “1”.

Top View

Truth Table

JKQ 0000
00Q
0 1 0 10 01

MM74C73 • MM74C76

tn = bit time before clock pulse
t

n+1

101 11Q
11Q

= bit time after clock pulse

Logic Diagrams

t

n

t

n+1

n

n

Preset Clear

01 10

Note 1: No change in output from previous state

Q

n

n

(Note 1) (Note 1)

Q

n

Q

n

MM74C73

MM74C76

Transmission Gate

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Absolute Maximum Ratings(Note 2)

Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range
Storage Temperature

−55°C to +125°C

−65°C to +150°C

Power Dissipation

Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature

(Soldering, 10 seconds) 260

Operating V

(Max) 18V

V

CC

Range +3V to 15V

CC

Note 2: “Absolute Maximum Ratings” are those values bey ond which the
safety of the device cannot be guaranteed. Except for “Operating T empera­ture Range” they are not meant to imply that the devic es should be oper-

°C

ated at these limits. The table of Electrical Characteristics provides
conditions for actual device operation.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

V

IN(0)

V

OUT(1)

V

OUT(0)

I

IN(1)

I

IN(0)

I

CC

LOW POWER TTL TO CMOS INTERFACE

V

IN(1)

V

IN(0)

V

OUT(1)

V

OUT(0)

OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)

I

SOURCE

I

SOURCE

I

SINK

I

SINK

Logical “1” Input Voltage VCC = 5V 3.5

VCC = 10V 8

Logical “0” Input Voltage VCC = 5V 1.5

V

= 10V 2

CC

Logical “1” Output Voltage VCC = 5V 4.5

VCC = 10V 9

Logical “0” Output Voltage VCC = 5V 0.5

= 10V 1

V

CC

Logical “1” Input Current VCC = 15V 1 µA
Logical “0” Input Current VCC = 15V −1 µA
Supply Current VCC = 15V 0.050 60 µA

Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V
Logical “0” Input Voltage VCC = 4.75V 0.8 V
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V

Output Source Current VCC = 5V, V

TA = 25°C, V

Output Source Current VCC = 10V, V

TA = 25°C, V

Output Sink Current VCC = 5V, V

TA = 25°C, V

Output Sink Current VCC = 10V, V

TA = 25°C, V

IN(0)

OUT

OUT

IN(1)

OUT

OUT

IN(0)

IN(1)

= 0V

= 0V

= 0V

= 0V

= 5V

= V

= 10V

= V

−1.75 mA

−8mA

CC

CC

1.75 mA

8mA

MM74C73 • MM74C76

V

V

V

V

3 www.fairchildsemi.com

AC Electrical Characteristics (Note 3)

T

= 25°C, C

A

Symbol Parameter Conditions Min Typ Max Units

C

IN

t

, t

pd0

pd1

t

pd0

t

pd

MM74C73 • MM74C76

t

S

t

H

t

PW

t

PW

t

MAX

tr, t

f

Note 3: AC Parameters are gu aranteed by DC correlated testing.

= 50 pF, unless otherwise noted

L

Input Capacitance Any Input 5 pF
Propagation Delay Time to a VCC = 5V 180 300
Logical “0” or Logical “1” from V

= 10V 70 110

CC

Clock to Q or Q
Propagation Delay Time to a VCC = 5V 200 300
Logical “0” from Preset or Clear V

= 10V 80 130

CC

Propagation Delay Time to a VCC = 5V 200 300
Logical “1” from Preset or Clear VCC = 10V 80 130
Time Prior to Clock Pulse that VCC = 5V 110 175
Data must be Present V

= 10V 45 70

CC

Time after Clock Pulse that J VCC = 5V −40 0
and K must be Held V

= 10V −20 0

CC

Minimum Clock Pulse Width VCC = 5V 120 190
tWL = t

WH

VCC = 10V 50 80
Minimum Preset and Clear VCC = 5V 90 130
Pulse Width VCC = 10V 40 60
Maximum Toggle Frequency VCC = 5V 2.5 4

VCC = 10V 7 11
Clock Pulse Rise and Fall Time VCC = 5V 15

VCC = 10V 5

ns

ns

ns

ns

ns

ns

ns

MHz

µs

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AC Test Circuit Switching Time Waveforms

CMOS to CMOS

tr = tf = 20 ns

Typical Applications

Ripple Binary Counters

MM74C73 • MM74C76

Shift Registers

74C Compatibility Guaranteed Noise Margin

5 www.fairchildsemi.com

as a Function of V

CC

Physical Dimensions inches (millimeters) unless otherwise noted

MM74C73 • MM74C76

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number N14A

Package Number M16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be rea­sonably expected to result in a significant injury to the
user.

Package Number N16E

2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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