Fairchild MM74C373, MM74C374 service manual

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MM74C373 • MM74C374
3-STATE Octal D-Type Latch •

3-STATE Octal D-Type Flip-Flop

MM74C373 • MM74C374 3-STATE Octal D-T ype Latch • 3-STATE Octal D-Type Flip-Flop

October 1987
Revised January 1999

General Description

The MM74C373 and MM74C374 are integrated, comple­mentary MOS (CMOS), 8-bit storage elements with 3­STATE outputs. These outputs have been specially
designed to drive high capaci tive loads, such as on e might
find when driving a bus, and to have a fan out of 1 when
driving standard TT L. When a high l ogic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what sig nals are prese nt at
the other inputs and the state of the storage elements.

The MM74C373 is an 8-bit latch. When LATCH
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH

The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D input s, meeting the set-up and hold
time requirements, is transferred to th e Q outpu ts on posi­tive-going transitions of the CLOCK input.

ENABLE returns high again.

ENABLE is

Both the MM74C373 and the MM74C374 are being assem-

bled in 20-pin dual-i n-line packages with 0.300” pin cen­ters.

Features

■ Wide supply voltage range: 3V to 15V

■ High noise immunity: 0.45 V

■ Low power consumption

■ TTL compatibility:

Fan out of 1driving standard TTL

■ Bus driving capability

■ 3-STATE outputs

■ Eight storage elements in one package

■ Single CLOCK/LATCH

ABLE control inputs

■ 20-pin dual-in-line package with 0.300” centers takes
half the board space of a 24-pin package

(typ.)

CC

ENABLE and OUTPUT DIS-

Ordering Code:

Order Number Package Number Package Description

MM74C373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C374M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.

© 1999 Fairchild Semiconductor Corporation DS005906.prf www.fairchildsemi.com

Connection Diagrams

MM74C373

MM74C373 • MM74C374

Pin Assignments for DIP and SOIC

MM74C374

Top View

Truth Tables

MM74C373 MM74C374

Output LATCH DQ

Disable ENABLE

LHHH
LHLL
LLXQ
H X X Hi-Z

L = LOW logic level
H = HIGH logic level
X = Irrelevant



= LOW-to-HIGH logic level transition
Q = Preexisting output level
Hi-Z = High impedance output state

Top View

Output Clock D Q

Disable

L
L
LLXQ
LHXQ
H X X Hi-Z




HH
LL

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Block Diagrams

MM74C373 • MM74C374

MM74C373 (1 of 8 Latches)

MM74C374 (1 of 8 Flip-Flops)

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Absolute Maximum Ratings(Note 1)

Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range (T

MM74C373 −40°C to +85°C
Storage Temperature Range (T
Power Dissipation

Dual-In-Line 700 mW

Small Outline 500 mW

MM74C373 • MM74C374

DC Electrical Characteristics

)

A

) −65°C to +150°C

S

Operating V
Absolute Maximum V
Lead Temperature (T

(Soldering, 10 seconds) 260°C

Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the
safety of the device cannot be guaranteed. Ex ce pt for “O perating Tempera­ture Range” they are not mean t to imply that the devices sho uld be oper­ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device op eration.

Range 3V to 15V

CC

CC

)

L

Min/Max limits apply across temperature range unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5V 3.5 V

VCC = 10V 8.0 V

V

IN(0)

Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2.0 V

V

OUT(1)

Logical “1” Output Voltage VCC = 5V, IO = −10 µA4.5 V

VCC = 10V, IO = −10 µA9.0 V

V

OUT(0)

Logical “0” Output Voltage VCC = 5V, IO = 10 µA0.5V

VCC = 10V, IO = 10 µA1.0V
I
I
I

IN(1)
IN(0)
OZ

Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA
Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA
3-STATE Leakage Current VCC = 15V, VO = 15V 0.005 1.0 µA

VCC = 15V, VO = 0V −1.0 −0.005 µA
I

CC

Supply Current VCC = 15V 0.05 300 µA

CMOS/LPTTL INTERFA CE

V

IN(1)

V

IN(0)

V

OUT(1)

Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V
Logical “0” Input Voltage VCC = 4.75V 0.8 V
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µAV

− 0.4 V

CC

VCC = 4.75V, IO = −1.6 mA 2.4 V
V

OUT(0)

Logical “0” Output Voltage VCC = 4.75V, IO = 1.6 mA 0.4 V

OUTPUT DRIVE (Short Circuit Current)

I

SOURCE

Output Source Current VCC = 5V, V

= 0V −12 −24 mA

OUT

TA = 25°C (Note 2)
I

SOURCE

Output Source Current VCC = 10V, V

= 0V −24 −48 mA

OUT

TA = 25°C (Note 2)
I

SINK

Output Sink Current VCC = 5V, V

OUT

= V

CC

612 mA

(N-Channel) TA = 25°C (Note 2)

I

SINK

Output Sink Current VCC = 10V, V

OUT

= V

CC

24 48 mA

(N-Channel) TA = 25°C (Note 2)

Note 2: These are peak output current capabilities. Continuous output current is rated at 12 mA max.

18V

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