Fairchild MM74C32 service manual
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MM74C32
Quad 2-Input OR Gate
MM74C32 Quad 2-Input OR Gate
October 1987
Revised January 1999
General Description
The MM74C32 employs complementary MOS (CMOS)
transistors to achieve low power and hi gh noise margin,
these gates provide the ba sic functions us ed in the impl ementation of digital integrated circuit systems. The N- and
P-channel enhancemen t mode transistors provide a sym metrical circuit with output swings essentially equal to the
supply voltage. This results in high noise immunity over a
wide supply voltage ran ge. No DC power other than th at
caused by leakage current is c onsumed dur ing static co n-
ditions. All inputs are protected against static discharge
damage.
Features
■ Wide supply voltage range: 3.0V to 15V
■ Guaranteed noise margin: 1.0V
■ High noise immunity: 0.45V V
■ Low power TTL compatibility: fan out of 2 driving 74L
CC
(typ.)
Ordering Code:
Order Number Package Number Package Description
MM74C32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the or dering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
© 1999 Fairchild Semiconductor Corporation DS005881.prf www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range −40°C to +85°C
MM74C32
Storage Temperature Range −65°C to +150°C
Power Dissipa tion (P
Dual-In-Line 700 mW
)
D
Absolute Maximum V
CC
Lead Temperature
(Soldering, 10 seconds) 260°C
Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the
safety of the device cannot be guaranteed. Ex ce pt for “Operating Temperature Range” they are not mean t to imply that the devices sho uld be operated at these limits. The Electrical Charac t eristics table provides co nditions
for actual device operation.
Small Outline 500 mW
Operating V
Range 3.0V to 15V
CC
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Logical “1” Input Voltage VCC = 5.0V 3.5 V
VCC = 10V 8.0 V
Logical “0” Input Voltage VCC = 5.0V 1.5 V
VCC = 10V 2.0 V
Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA4.5 V
VCC = 10V, IO = −10 µA9.0 V
Logical “0” Output Voltage VCC = 5.0V, IO = 10 µA0.5V
VCC = 10V, IO = 10 µA1.0V
Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA
Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA
Supply Current VCC = 15V 0.05 15 µA
Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V
Logical “0” Input Voltage VCC = 4.75V 0.8 V
Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V
Output Source Current VCC = 5.0V, V
= 0V −1.75 −3.3 mA
OUT
(P-Channel)
Output Source Current VCC = 10V, V
= 0V −8.0 −15 mA
OUT
(P-Channel)
Output Sink Current VCC = 5.0V, V
OUT
= V
CC
1.75 3.6 mA
(N-Channel)
Output Sink Current VCC = 10V, V
OUT
= V
CC
8.0 16 mA
(N-Channel)
18V
AC Electrical Charac teristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
t
pd
C
IN
C
PD
Note 2: AC Parameters are guara nt eed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C
AN-90.
www.fairchildsemi.com 2
Propagation Delay Time to VCC = 5.0V 80 150 ns
Logical “1” or “0” VCC = 10V 35 70 ns
Input Capacitance Any Input (Note 3) 5 pF
Power Dissipation Capacitance Per Gate (Note 4) 15 pF
determines t he no loa d AC power c ons um ption of a ny CM OS d evice. For com plet e expla natio n se e Family Cha ract eris tics Appl icat ion N ote —
PD
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