Fairchild HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 service manual

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HUF75639G3, HUF75639P3, HUF75639S3S,
HUF75639S3
Data Sheet December 2001
56A, 100V, 0.025 Ohm, N-Channel UltraFET Power MOSFETs
These N-Channel pow er MOSFETs are manufactured using the innovat ive Ul traFET® pr ocess . This
Formerly developmental type TA75639.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75639G3 TO-247 75639G HUF75639P3 TO-220AB 75639P HUF75639S3S TO-263AB 75639S HUF75639S3 TO-262AA 75639S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75639S3ST.
Features
• 56A, 100V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™ Electrical Models
- Spice and Saber Thermal Impedance M ode ls
- www.fairchildsemi.com
• Peak Current vs Pulse Width C urve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC STYLE TO-247 JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(TAB)
JEDEC TO-263AB TO-262AA
GATE
SOURCE
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
DRAIN (FLANGE)
For severe environments, see our Automotive HUFA series.
DRAIN
(FLANGE)
DRAIN
(TAB)
SOURCE
SOURCE
DRAIN
GATE
DRAIN
GATE
©2001 Fairchild Semiconductor Corpo ration HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Rev. B
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
= 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
DGR
GS
100 V 100 V ±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
, T
J
STG
D
AS
D
56
Figure 4
Figures 6, 14, 15
200
1.35
-55 to 175
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
300 260
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. T
= 25oC to 150oC.
J
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
DSSID
DSS
GSS
= 250µA, VGS = 0V (Figure 11) 100 - - V
VDS = 95V, VGS = 0V - - 1 µA
= 90V, VGS = 0V, TC = 150oC--250µA
V
DS
VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V Drain to Source On Resistance r
GS(TH)VGS
DS(ON)ID
= VDS, ID = 250µA (Figure 10) 2 - 4 V
= 56A, VGS = 10V (Figure 9) - 0.021 0.025
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V
GS
= 10V) Turn-On Time t Turn-On Delay Time t
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Turn-Off Time t
θJC θJA
ON
r
f
OFF
(Figure 3) - - 0.74 TO-247 - - 30 TO-220, TO-263 - - 62
VDD = 50V, ID 56A,
= 0.89Ω, VGS = 10V,
R
L
R
= 5.1
GS
--110ns
-15- ns
-60- ns
-20- ns
-25- ns
- - 70 ns
o
C/W
o
C/W
o
C/W
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q Gate Charge at 10V Q Threshold Gate Charge Q Gate to Source Gate Charge Q Gate to Drain “Miller” Charge Q
g(TOT)VGS
g(10)
g(TH)
gs gd
= 0V to 20V VDD = 50V,
56A,
I
VGS = 0V to 10V - 57 75 nC VGS = 0V to 2V - 3.7 4.5 nC
D
= 0.89
R
L
I
g(REF)
= 1.0mA
(Figure 13)
- 110 130 nC
-9.8- nC
-24-nC
©2001 Fairchild Semiconductor Corpo ration HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Rev. B
5
5
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V Reverse Recovery Time t Reverse Recovered Charge Q
Typical Performance Curves
1.2
1.0
0.8
ISS
OSS
RSS
SD
rr
RR
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
- 2000 - pF
- 500 - pF
-65-pF
ISD = 56A - - 1.25 V ISD = 56A, dISD/dt = 100A/µs - - 110 ns ISD = 56A, dISD/dt = 100A/µs - - 320 nC
60
50
40
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
TC, CASE TEMPERATURE (oC)
125
FIGURE 1. NORMALIZED POWER DISSIPATI ON vs CASE
TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
θJC
Z
THERMAL IMPEDANCE
SINGLE PULSE
0.01
-5
10
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
30
20
, DRAIN CURRENT (A)
D
I
10
0
17
25 50 75 100 125 150 17
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
P
DM
t
1
t
x R
θJC
+ T
2
C
1
10
NOTES: DUTY FACTOR: D = t PEAK TJ = PDM x Z
-2
10
-1
10
10
θJC
1/t2
0
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corpo ration HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Rev. B
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