Fairchild FST32211 service manual
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FST32211
40/48-Bit Bus Switch
FST32211 40/48-Bit Bus Switch
April 2001
Revised July 2002
General Description
The Fairchild Switch FST32211 provides up to 48-bits of
high-speed CMOS TTL- compatible bu s switching. T he low
On Resistance of the switch all ows input s to be conn ect ed
to outputs without adding pr opagation delay or gene rating
additional ground bounce noise.
The device can be organize d as four 12-bit, two 24-bit, or
one 48-bit bus swit ch. When routed as a 40-bi t bu s sw it ch,
the device can be orga nized as four 10-bit, two 20 -bit or
one 40-bit bus switch. When OE
and Port 1A is connected to Por t 1B. When OE
the switch is ON and Port 2A is connected to Port 2B.
When OE
nected to Port 3B. When OE
Port 4A is connected to Port 4B. When OE
OE
A and B Ports.
is LOW, the switch is ON and Port 3A is con-
3
are HIGH, a hig h im pe dan ce state exists betw ee n t he
4
is LOW, the switch is ON
1
is LOW, the switch is ON and
4
is LOW,
2
, OE2, OE3, or
1
Features
■ 4Ω switch connection between two ports
■ Minimal propagation delay through the switch
■ Low l
CC
■ Zero bounce in flow-through mode
■ Control inputs compatible with TTL level
■ Packaged in plastic Fine Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number Package Number Package Description
FST32211G
(Note 1)(Note 2)
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Logic Diagram
© 2002 Fairchild Semiconductor Corporation DS500404 www.fairchildsemi.com
Connection Diagram
FST32211
(Top Thru View)
Pin Descriptions
Pin Name Description
OE
, OE2, OE3, OE
1
1A, 2A, 3A, 4A Bus A
1B, 2B, 3B, 4B Bus B
FBGA Pin Assignments
(40-Bit Routing)
123 4 56
A 1A
B 1A41A3GND OE11B31B
C 1A61A5GND GND 1B51B
D 1A81A7GND GND 1B71B
E 1A101A9V
F 2A22A1V
G 2A42A3V
H 2A62A5GND GND 2B52B
J 2A82A72A92B
K 2A103A10GND GND 3B102B
L 3A93A8GND GND 3B83B
M 3A73A6GND V
N 3A53A4V
P 3A33A2V
R 3A14A10GND GND 4B103B
T 4A94A8GND GND 4B84B
U 4A74A6GND 4B
V 4A54A44A1OE44B44B
W 4A34A2OE3NC 4B24B
1A1NC OE21B11B
2
CCVCC
CCVCC
GND 2B32B
CC
9
CC
CCVCC
CCVCC
1
1B91B
2B12B
2B72B
3B63B
3B43B
3B23B
4B64B
2
4
6
8
10
2
4
6
8
10
9
7
5
3
1
9
7
5
3
Truth Tables
Inputs Inputs/Outputs
Bus Switch Enables
4
OE
1
LL1A
LH1A
HLZ2A
HHZZ
OE
3
LL3A
LH3A
HLZ4A
HHZZ
OE
2
1A, 1B 2A, 2B
= 1B 2A = 2B
= 1B Z
Inputs Inputs/Outputs
OE
4
3A, 3B 4A, 4B
= 3B 4A = 4B
= 3B Z
= 2B
= 4B
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