Fairchild FDMS3606AS service manual

FDMS3606AS

Q

Power 56

G1

D1

G2

S2

D1

PHASE (S1/D2)

S2

S2 S2 G2

D1

D1 D1

G1

Top Bottom

PHASE

PowerTrench® Power Stage

30 V Asymmetric Dual N-Channel MOSFET

Features

Q1: N-Channel

 Max r  Max r

Q2: N-Channel

 Max r  Max r

 Low inductance packaging shortens rise/fall times, resulting in

lower switching losses

 MOSFET integration enables optimum layout for lower circuit

inductance and reduced switch node ringing

 RoHS Compliant

= 8 mΩ at VGS = 10 V, ID = 13 A

DS(on)

= 11 mΩ at VGS = 4.5 V, ID = 11 A

DS(on)

= 1.9 mΩ at VGS = 10 V, ID = 27 A

DS(on)

= 2.8 mΩ at VGS = 4.5 V, ID = 23 A

DS(on)

General Description

This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency.

Applications

 Computing  Communications  General Purpose Point of Load  Notebook VCORE

September 2011

FDMS3606AS PowerTrench

®

Power Stage

 Sever

2

5 6 7 8

MOSFET Maximum Ratings T

Symbol Parameter Q1 Q2 Units

V

DS

V

GS

I

D

E

AS

P

D

TJ, T

STG

Drain to Source Voltage 30 30 V Gate to Source Voltage (Note 3) ±20 ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 30 40

-Continuous (Silicon limited) T

-Continuous T

-Pulsed 40 100 Single Pulse Avalanche Energy 40 Power Dissipation for Single Operation TA = 25 °C 2.2 Power Dissipation for Single Operation T Operating and Storage Junction Temperature Range -55 to +150 °C

= 25 °C unless otherwise noted

A

= 25 °C 60 148

C

= 25 °C 13

A

= 25 °C 1.0

A

1a

4 1a 1c

1

27

162

2.5

1.0

4 3 2 1

1b

5 1b 1d

A

mJ

W

Thermal Characteristics

R

θJA θJA

R

θJC

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

Thermal Resistance, Junction to Ambient 57 Thermal Resistance, Junction to Ambient 125 Thermal Resistance, Junction to Case 3.5 2

22CA

N9CC

FDMS3606AS Power 56 13 ” 12 mm 3000 units

1

1a

1c

1b

50

1d

120

°C/WR

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FDMS3606AS PowerTrench

Electrical Characteristics T

= 25 °C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Off Characteristics

BV

ΔBV ΔT

I

DSS

I

GSS

DSS

DSS J

= 250 μA, VGS = 0 V

Drain to Source Breakdown Voltage Breakdown Voltage Temperature

Coefficient

D

I

= 1 mA, VGS = 0 V

D

ID = 250 μA, referenced to 25 °C I

= 10 mA, referenced to 25 °C

D

Zero Gate Voltage Drain Current VDS = 24 V, V Gate to Source Leakage Current,

Forward

V

= 20 V, VDS= 0 V

GS

= 0 V

Q1Q230

30

Q1 Q2

V

15 20

500μAμA 100

100nAnA

mV/°C

1

I

On Characteristics

V

GS(th)

ΔV ΔT

r

DS(on)

g

FS

GS(th)

J

Gate to Source Threshold Voltage Gate to Source Threshold Voltage

Temperature Coefficient

Drain to Source On Resistance

Forward Transconductance

= VDS, ID = 250 μA

GS

V

= VDS, ID = 1 mA

GS

ID = 250 μA, referenced to 25 °C I

= 10 mA, referenced to 25 °C

D

= 10 V, ID = 13 A

V

GS

V

= 4.5 V, ID = 11 A

GS

V

= 10 V , ID = 13 A , TJ = 125 °C

GS

V

= 10 V, ID = 27 A

GS

V

= 4.5 V, ID = 23 A

GS

V

= 10 V , ID = 27 A , TJ = 125 °C

GS

V

= 5 V, ID = 13 A

DS

V

= 5 V, ID = 27 A

DS

Q1Q21.1

1.121.8

Q1 Q2

Q1

Q2

Q1 Q2

-6

-5

5.8

8.5

7.8

1.4 2

1.9

61

154

2.7 3

mV/°C

8

11

10.8

1.9

2.8

V

mΩ

S

®

Power Stage

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Gate Resistance

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q

g

gs

gd

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

Total Gate Charge V

Gate to Source Gate Charge

Gate to Drain “Miller” Charge

Q1:

= 15 V, VGS = 0 V, f = 1 MHZ

V

DS

Q2:

= 15 V, VGS = 0 V, f = 1 MHZ

V

DS

Q1 Q2

Q1Q20.2

0.2

1273 4129

1527

1695 5490

461

615

2030

50 9875150

0.6

0.8

pF

2 3

Ω

8.21516 27

2.5

5.51011

20 36

32 58

2.2

3.41010

21 59

10 27

29 83

14 38

3.9

12

3.1

5.7

ns

nC

Q1:

= 15 V, ID = 13 A, R

V

DD

Q2:

= 15 V, ID = 27 A, R

V

DD

= 0 V to 10 V

GS

= 0 V to 4.5 V

GS

= 6 Ω

GEN

= 6 Ω

GEN

Q1 V

= 15 V,

DD

I

= 13 A

D

Q2 VDD = 15 V, I

= 27 A

D

Q1 Q2

2

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FDMS3606AS PowerTrench

Electrical Characteristics T

= 25 °C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Drain-Source Diode Characteristics

0.8

V

= 0 V, IS = 13 A (Note 2)

V

SD

t

rr

Q

rr

Notes: 1: R

θJA

by the user's board design.

Source to Drain Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R

a. 57 °C/W when mounted on

2

a 1 in

pad of 2 oz copper

c. 125 °C/W when mounted on a minimum pad of 2 oz copper

GS

V

= 0 V, IS = 27 A (Note 2)Q1Q2

GS

Q1 I

= 13 A, di/dt = 100 A/μs

F

Q2 I

= 27 A, di/dt = 300 A/μs

F

Q1 Q2

θJC

b. 50 °C/W when mounted on

2

a 1 in

pad of 2 oz copper

d. 120 °C/W when mounted on a minimum pad of 2 oz copper

is guaranteed by design while R

0.8 253940

9

571891

1.2

62

is determined

θCA

V

ns

nC

®

Power Stage

2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. 4: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A. 5: EAS of 162 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 18 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 27 A.

3

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FDMS3606AS PowerTrench

0.0 0. 2 0.4 0.6 0.8 1.0

0

10

20

30

40

VGS = 4.5 V

VGS = 3.5 V

V

GS

= 6 V

VGS = 4 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

VGS = 10 V

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 10203040

0

1

2

3

4

VGS = 6 V

VGS = 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

ID = 13 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

T

J

, JUNCTION TE MPERATU RE (

o

C)

246810

0

4

8

12

16

20

TJ = 125 oC

ID = 13 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA GE (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

1.5 2.0 2.5 3.0 3.5 4.0

0

10

20

30

40

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

40

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q1 N-Channel) T

Figure 1.

On Region Characteristics Figure 2.

= 25 °C unless otherwise noted

J

Norma lized O n - R e s i s t a n ce

vs Drain Current and Gate Voltage

®

Power Stage

Fig u r e 3. Nor m a lized On R esistan c e

vs Junction Temperature

Figure 5. Transfer Characteristics

Figure 4.

On-Resistance vs Gate to

Source Voltage

Figure 6.

Source to Drain Diode

Forward Voltage vs Source Current

4

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FDMS3606AS PowerTrench

0 5 10 15 20 25

0

2

4

6

8

10

ID = 13 A

V

DD

= 20 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 30

10

100

1000

2000

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.01 0.1 1 10 100

1

10

20

TJ = 100 oC

TJ = 25 oC

T

J

= 125

o

C

t

AV

, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

20

40

60

80

100

Limited by Package

V

GS

= 4.5 V

R

θJC

= 3.5 oC/W

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

C

, CASE TEMPERATURE (

o

C)

0.01 0.1 1 10 100

0.01

0.1

1

10

100

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS

LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

10s

100us

200

10-410-310-210

-1

110

100 1000

0.1

1

10

100

1000

SINGLE PULSE R

θJA

= 125

o

C/W

T

A

= 25

o

C

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q1 N-Channel) T

Figure 7.

Gate Charge Characteristics Figure 8.

= 25 °C unless otherwise noted

J

Capa c i t a nce v s D r ain

to Source Voltage

®

Power Stage

Figure 9.

Un c l a mp e d In d u c ti v e

Switching Capability

Figure 11. Forward Bias Safe

Operating Area

Figure 10. Maximum Continuous Drain

Current vs Case Temperature

Figure 12. Single Pulse Maximum

Power Dissipation

5

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FDMS3606AS PowerTrench

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.001

0.01

0.1

1

SINGLE PULSE R

θJA

= 125 oC/W

(Note 1c)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PU L SE D U R ATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

2

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

Typical Characteristics (Q1 N-Channel) T

Figure 13. Junction-to-Ambient Transient Thermal Response Curve

= 25 °C unless otherwise noted

J

®

Power Stage

6

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FDMS3606AS PowerTrench

0.00.20.40.60.81.0

0

20

40

60

80

100

VGS = 4.5 V

VGS = 3 V

V

GS

= 3.5 V

VGS = 4 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

VGS = 10 V

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

020406080100

0

2

4

6

8

VGS = 3 V

VGS = 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.8

1.0

1.2

1.4

1.6

ID = 27 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

T

J

, JUNCTION TEMPERATURE (

o

C)

246810

0

2

4

6

8

TJ = 125 oC

ID = 27 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA G E (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURA TION = 80 μs DUTY CYCLE = 0.5% MAX

1.5 2.0 2.5 3.0 3.5

0

20

40

60

80

100

TJ = 125 oC

V

DS

= 5 V

PULSE DURATION = 80 μs DUTY CY C L E = 0.5% MA X

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

100

TJ = -55 oC

TJ = 25 oC

TJ = 125 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q2 N-Channel) T

Figure 14. On-Region Characteristics

= 25 oC unlenss otherwise noted

J

Figure 15. Normalized on-Resistance vs Drain

Current and Gate V oltage

®

Power Stage

Figure 16. Normalized On-Resistance

vs Junction Temperature

Figure 18. Transfer Characteristics

Figure 17. On-Resistance vs Gate to

Source Voltage

Figure 19. Source to Drain Diode

Forward Voltage vs Source Current

7

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0 102030405060

0

2

4

6

8

10

ID = 27A

V

DD

= 20 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 30

10

100

1000

10000

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.01 0.1 1 10 100 1000

1

10

50

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

50

100

150

200

R

θJC

= 2 oC/W

V

GS

= 4.5 V

Limited by Package

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

C

, CASE TEMPERATURE (

o

C)

FDMS3606AS PowerTrench

0.01 0.1 1 10 100200

0.01

0.1

1

10

100

200

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS A REA IS

LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 120

o

C/W

T

A

= 25

o

C

10s

10

-3

10

-2

10

-1

110

100 1000

0.1

1

10

100

1000

SINGLE PULSE R

θJA

= 120

o

C/W

T

A

= 25

o

C

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q2 N-Channel) T

Figure 20. Gate Charge Characteristics

o

= 25

C unless otherwise noted

J

Figure 21. Capacitance vs Drain

to Source Voltage

®

Power Stage

Figure 22. Unclamped Inductive

Swit

ching Capability

Oper

ating Area

Figure 24. Forward Bias Safe

Figure 23. Maximun Continuous Drain

Current vs Case Temperature

Figure 25. Single Pulse Maximum

Power Dissipation

8

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FDMS3606AS PowerTrench

Figure 26. Junction-to-Ambient Transient Thermal Response Curve

10

-3

10

-2

10

-1

110

100 1000

0.001

0.01

0.1

1

2

SINGLE PULSE R

θJA

= 120 oC/W

(Note 1d)

DUTY CYCLE-DESCEND ING OR DER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

Typical Characteristics (Q2 N-Channel) T

= 25 oC unless otherwise noted

J

®

Power Stage

9

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Typical Characteristics (continued)

0 50 100 150 200 250 300

-5

0

5

10

15

20

25

30

didt = 300 A/μs

CURRENT (A)

TIME (ns)

0 5 10 15 20 25 30

10

-6

10

-5

10

-4

10

-3

10

-2

TJ = 125 oC

TJ = 100 oC

TJ = 25 oC

I

DSS

, REVERSE LEAKAGE CURRENT (A)

VDS, REVERSE VOLTAGE (V)

SyncFET Schottky body diode Characteristics

FDMS3606AS PowerTrench

Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3606AS.

Figure 27. FDMS3606AS SyncFET body

diode reverse recovery characteristic

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.

Figure 28. SyncFET body diode reverse leakage versus drain-source voltage

®

Power Stage

10

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Application Information

1. Switch Node Ringing Suppression

Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions.

FDMS3606AS PowerTrench

®

Power Stage

Power Stage Device

Competitors solution

Figure 29. Power Stage phase node rising edge, High Side Turn on

*Patent Pending

11

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Figure 30. Shows the Power Stage in a buck converter topology

FDMS3606AS PowerTrench

®

Power Stage

2. Recommended PCB Layout Guidelines

As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.

Figure 31. Recommended PCB Layout

12

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Following is a guideline, not a requirement which the PCB designer should consider:

1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application.

2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage.

3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness.

4. The PowerTrench part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high-frequency ringing.

5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-fre quency opera tion this imp edance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional sw itching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part.

®

Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the

FDMS3606AS PowerTrench

®

Power Stage

6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.

7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias.

13

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Dimensional Outline and Pad Layout

FDMS3606AS PowerTrench

®

Power Stage

14

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TRADEMARKS

tm

®

tm

™

tm

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semi conductor and/or its glob al subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

2Cool™ AccuPower™ Auto-SPM™ AX-CAP™*

®

BitSiC Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED Dual Cool™ EcoSPARK EfficentMax™

®

ESBC™

®

Fairchild Fairchild Semiconductor FACT Quiet Series™

®

FACT

®

FAST FastvCore™ FETBench™

®

FlashWriter FPS™ F-PFS™ FRFET Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™ Motion-SPM™ mWSaver™ OptiHiT™ OPTOLOGIC OPTOPLANAR

®

*

®

PDP SPM™ Power-SPM™ PowerTrench PowerXS™

SM

Programmable Active Droop™ QFET QS™ Quiet Series™ RapidConfigure™

®

Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™

®

SPM STEALTH™ SuperFET SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS SyncFET™ Sync-Lock™

®

®*

The Power Franchise The Right Technology for Your Success™

TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TranSiC TriFault Detect™ TRUECURRENT μSerDes™

UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™

®

*

FDMS3606AS PowerTrench

®

Power Stage

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry. All ma nufactures of semiconductor products are exper iencing counterfeiting of their

parts. Customers who inadvertently purchase counterfeit parts experience many proble ms su ch as loss of brand repu tation , substa ndard pe rfo rmance, f aile d application, and increased cost of production and manufacturing delays. Fairchild is takin g stron g measures to protect ourselves and our customers from th e proliferation of counterfeit parts. Fairchild str ongly encourages customers t o purchase Fairchild par ts either d irectly from Fairchild o r from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping t his practice by buying direct or from authorized distributor s.

PRODUCT STATUS DEFINITIONS Definition of Terms

.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to ca use the failure of the life support device or system, or to affect its safety or effectiveness.

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications fo r product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

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www.fairchildsemi.com

Rev. I55

Fairchild FDMS3606AS service manual

Specifications and Main Features

Frequently Asked Questions

User Manual