Datasheet FDMF6707C Datasheet (Fairchild)

March 2012

FDMF6707C - Extra-Small, High-Performance, HighFrequency DrMOS Module

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Benefits

 Ultra-Compact 6x6mm PQFN, 72% Space-Saving

Compared to Conventional Discrete Solutions

 Fully Optimized System Efficiency  Clean Switching Waveforms with Minimal Ringing  High-Current Handling

Features

 Over 93% Peak-Efficiency  High-Current Handling of 50A  High-Performance PQFN Copper-Clip Package  3-State 5.0V PWM Input Driver  Skip-Mode SMOD# (Low-Side Gate Turn Off) Input  Thermal Warning Flag for Over-Temperature

Condition

 Driver Output Disable Function (DISB# Pin)  Internal Pull-Up and Pull-Down for SMOD# and

DISB# Inputs, Respectively

 Fairchild PowerTrench

Clean Voltage Waveforms and Reduced Ringing

®

Technology MOSFETs for

 Fairchild SyncFET™ (Integrated Schottky Diode)

Technology in the Low-Side MOSFET

 Integrated Bootstrap Schottky Diode  Adaptive Gate Drive Timing for Shoot-Through

Protection

 Under-Voltage Lockout (UVLO)  Optimized for Switching Frequencies up to 1MHz  Low-Profile SMD Package  Fairchild Green Packaging and RoHS Compliance  Based on the Intel

®

4.0 DrMOS Standard

Description

The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, integrated MOSFET plus driver power stage solution for high-current, high-frequency, synchronous buck DC-DC applications. The FDMF6707C integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm PQFN package.

With an integrated approach, the complete switching power stage is optimized for driver and MOSFET dynamic performance, system inductance, and power MOSFET R performance PowerTrench which dramatically reduces switch ringing, eliminating the snubber circuit in most buck converter applications.

A new driver IC with reduced dead times and propagation delays further enhances performance. A thermal warning function indicates potential overtemperature situations. FDMF6707C also incorporates features such as Skip Mode (SMOD) for improved lightload efficiency, along with a three-state 5V PWM input for compatibility with a wide range of PWM controllers.

. XS™ DrMOS uses Fairchild's high-

DS(ON)

®

MOSFET technology,

Applications

 High-Performance Gaming Motherboards  Compact Blade Servers, V-Core and Non-V-Core

DC-DC Converters

 Desktop Computers, V-Core and Non-V-Core

DC-DC Converters

 Workstations  High-Current DC-DC Point-of-Load (POL)

Converters

 Networking and Telecom Microprocessor Voltage

Regulators

 Small Form-Factor Voltage Regulator Modules

Ordering Information

Part Number Current Rating Package Top Mark

FDMF6707C 50A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0mm Package FDMF6707C

Typical Application Circuit

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

V5V

C

VDRV

DISB#

2.2V

OFF

ON

Open Drain Output

DrMOS Block Diagram

VCIN VIN

VDRV

R

DISB#

PWM

SMOD#

THWN#

FDMF6707C

CGND

PGND

BOOT

PHASE

VSWH

BOOT

Figure 1. Typical Application Circuit

VDRV

VIN 3V ~ 15V

C

VIN

C

BOOT

V

L

OUT

C

OUT

BOOT

VIN

VCIN

DISB#

PWM

THWN#

R

UP_PWM

R

DN_PWM

CGND

10µA

UVLO

V

CIN

Temp.

Sense

Input

3- State

Logic

D

Boot

GH

Logic

Level Shift

Dead-Time

Control

GL

Logic

V

CIN

10µA

SMOD#

Figure 2. DrMOS Block Diagram

Q1 HS Power MOSFET

GH

30kΩ

PHASE

VSWH

V

DRV

GL

30kΩ

Q2 LS Power MOSFET

PGND

Pin Configuration

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW,

1 SMOD#

2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.

3 VDRV

4 BOOT

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float; must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43

16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.

36 GL For manufacturing test only. This pin must float; must not be connected to any pin.

38 THWN#

39 DISB#

40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller.

VSWH

the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor.

Power for gate driver. Minimum 1µF ceramic capacitor is recommended, connected as close as possible from this pin to CGND.

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE.

No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience.

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module.

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor.

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V

Supply Voltage Referenced to CGND -0.3 6.0 V

CIN

V

Drive Voltage Referenced to CGND -0.3 6.0 V

DRV

V

Output Disable Referenced to CGND -0.3 6.0 V

DISB#

V

PWM Signal Input Referenced to CGND -0.3 6.0 V

PWM

V

Skip Mode Input Referenced to CGND -0.3 6.0 V

SMOD#

VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V

V

Thermal Warning Flag Referenced to CGND -0.3 6.0 V

THWN#

VIN Power Input Referenced to PGND, CGND -0.3 25.0 V

V

Bootstrap Supply

BOOT

VGH High Gate Manufacturing Test Pin

V

PHASE Referenced to CGND -0.3 25.0 V

PHS

V

Switch Node Input

SWH

V

Bootstrap Supply Referenced to VDRV 22 V

BOOT

I

THWN# Sink Current -0.1 7.0 mA

THWN#

I

O(AV)

θ

JPCB

Output Current

Junction-to-PCB Thermal Resistance 3.5 °C/W

(1)

TA Ambient Temperature Range -40 +125 °C

TJ Maximum Junction Temperature +150 °C

T

Storage Temperature Range -55 +150 °C

STG

ESD Electrostatic Discharge Protection

Note:

1. I

is rated using Fairchild’s DrMOS evaluation board, TA = 25°C, natural convection cooling. This rating is limited

O(AV)

by the peak DrMOS temperature, T

= 150°C, and varies depending on operating conditions and PCB layout. This

J

rating can be changed with different application settings.

Referenced to VSWH, PHASE -0.3 6.0 V

Referenced to CGND -0.3 25.0 V

Referenced to VSWH, PHASE -0.3 6.0 V

Referenced to CGND -0.3 25.0 V

Referenced to PGND, CGND (DC Only) -0.3 25.0 V

Referenced to PGND, <20ns -8.0 25.0 V

fSW=300kHz, VIN=12V, V

fSW=1MHz, VIN=12V, VO=1V 45

Human Body Model, JESD22-A114 2000

Charged Device Model, JESD22-C101 1000

=1V 50

O

A

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

V

Control Circuit Supply Voltage 4.5 5.0 5.5 V

CIN

V

Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V

DRV

VIN Output Stage Supply Voltage 3.0 12.0 15.0

Note:

2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application

Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.

(2)

V

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Basic Operation

IQ Quiescent Current IQ=I

UVLO UVLO Threshold V

UVLO

PWM Input (V

R

V

t

D_HOLD-OFF

V

HiZ_PWM

PWM Input (V

R

V

t

D_HOLD-OFF

V

HiZ_PWM

DISB# Input

V

t

PD_DISBL

t

PD_DISBH

SMOD# Input

V

IH_SMOD

V

t

PD_SLGLL

t

PD_SHGLH

UVLO Hysteresis

_Hyst

= V

CIN

Pull-Up Impedance

UP_PWM

Pull-Down Impedance 10 kΩ

DN_PWM

PWM High Level Voltage 3.04 3.55 4.05 V

IH_PWM

3-State Upper Threshold 2.95 3.45 3.94 V

TRI_HI

3-State Lower Threshold 0.98 1.25 1.52 V

TRI_LO

PWM Low Level Voltage 0.84 1.15 1.42 V

IL_PWM

= 5V ±10%)

DRV

3-State Shut-off Time 160 200 ns

3-State Open Voltage 2.2 2.5 2.8 V

= V

CIN

Pull-Up Impedance 10 kΩ

UP_PWM

Pull-Down Impedance 10 kΩ

DN_PWM

PWM High Level Voltage

IH_PWM

3-State Upper Threshold

TRI_HI

3-State Lower Threshold

TRI_LO

PWM Low Level Voltage

IL_PWM

= 5V ±5%)

DRV

3-State Shut-Off Time 160 200 ns

3-State Open Voltage 2.3 2.5 2.7 V

High-Level Input Voltage 2 V

IH_DISB

Low-Level Input Voltage 0.8 V

IL_DISB

I

Pull-Down Current 10 µA

PLD

Propagation Delay

High-Level Input Voltage 2 V

Low-Level Input Voltage 0.8 V

IL_SMOD

I

Pull-Up Current 10 µA

PLU

Propagation Delay

= 5V, V

CIN

= 5V, and T

DRV

VCIN+IVDRV

Rising 2.9 3.1 3.3 V

CIN

= +25°C unless otherwise noted.

A

, PWM=LOW or HIGH or Float 2 mA

0.4 V

10 kΩ

3.22 3.55 3.87

3.13 3.45 3.77

1.04 1.25 1.46

0.90 1.15 1.36

PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH

PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH

25 ns

10 ns

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

V

Continued on the following page…

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Electrical Characteristics (Continued)

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Thermal Warning Flag

T

Activation Temperature 150 °C

ACT

T

Reset Temperature 135 °C

RST

R

Pull-Down Resistance I

THWN

250ns Timeout Circuit

t

D_TIMEOUT

High-Side Driver

R

SOURCE_GH

R

t

D_DEADON

t

PD_PLGHL

t

PD_PHGHH

t

PD_TSGHH

Low-Side Driver

R

SOURCE_GL

R

t

D_DEADOFF

t

PD_PHGLL

t

PD_TSGLH

Boot Diode

Timeout Delay

Output Impedance, Sourcing Source Current=100mA 1 Ω

Output Impedance, Sinking Sink Current=100mA 0.8 Ω

SINK_GH

t

Rise Time GH=10% to 90%, C

R_GH

t

Fall Time GH=90% to 10%, C

F_GH

LS to HS Deadband Time

PWM LOW Propagation Delay

PWM HIGH Propagation Delay (SMOD# Held LOW)

Exiting 3-State Propagation Delay

Output Impedance, Sourcing Source Current=100mA 1 Ω

Output Impedance, Sinking Sink Current=100mA 0.5 Ω

SINK_GL

t

Rise Time GL=10% to 90%, C

R_GL

t

Fall Time GL=90% to 10%, C

F_GL

HS to LS Deadband Time

PWM-HIGH Propagation Delay

Exiting 3-State Propagation Delay

VF Forward-Voltage Drop IF=10mA 0.35 V

VR Breakdown Voltage IR=1mA 22 V

= 5V, V

CIN

= 5V, and TA = +25°C unless otherwise noted.

DRV

=5mA 30 Ω

PLD

SW=0V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH

=1.1nF 6 ns

LOAD

=1.1nF 5 ns

LOAD

GL going LOW to GH going HIGH, 1V GL to 10 % GH

PWM going LOW to GH going LOW, V

IL_PWM

to 90% GH

PWM going HIGH to GH going HIGH, V

to 10% GH (SMOD#=LOW)

IH_PWM

PWM (from 3-State) going HIGH to GH going HIGH, V

IH_PWM

to 10% GH

=5.9nF 20 ns

LOAD

=5.9nF 13 ns

LOAD

SW going LOW to GL going HIGH,

2.2V SW to 10% GL

PWM going HIGH to GL going LOW, V

IH_PWM

to 90% GL

PWM (from 3-State) going LOW to GL going HIGH, V

IL_PWM

to 10% GL

250 ns

10 ns

16 30 ns

30 ns

12 ns

9 25 ns

20 ns

Timing Diagram

VSW

V

IH_PWM

PWM

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

V

IL_PWM

GL

GH

to

VSWH

90%

1.0V 10%

90%

H

t

PD PHGLL

t D_DEADON

10%

t

PD PLGHL

Figure 5. PWM Timing Diagram

1.2V

t

D_DEADOFF

t

D_TIMEOUT

( 250ns Timeout)

2.2V

Typical Performance Characteristics

Test Conditions: VIN=12V, V unless otherwise specified.

=1.0V, V

OUT

CIN

=5V, V

DRV

=5V, L

=320nH, TA=25°C, and natural convection cooling;

OUT

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

55 50 45

(A)

40

OUT

35 30 25 20 15

VIN= 12V, V

10

5

Module Output cur rent , I

0

0 25 50 75 100 125 150

Θ

JPCB

= 3.5°C/W

OUT

fSW= 1MHz

fSW= 300kHz

= 1.0V

PCB Temperature (°C)

Figure 6. Safe Operating Area Figure 7. Module Power Loss vs. Output Current

1.5

I

= 30A

OUT

1.4

1.3

1.2

11

10

9 8 7 6 5 4 3 2

Module Power Loss (W)

1 0

1.3

1.2

1.1

300kHz

500kHz

800kHz

1MHz

0 5 10 15 20 25 30 35 40 45

Module Output Curr ent, I

I

= 30A, fSW= 300kHz

OUT

(A)

1.1

1.0

1

Norm a liz e d Mo dule P owe r Los s

0.9 200 3 00 400 500 600 700 800 900 1000

Module Switching Fre quency, fSW(kHz)

Norma lize d Module P ower Los s

0.9 4 6 8 10 12 14 16

Module Input V olta ge, VIN(V)

Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage

1.10

1.05

1.00

0.95

I

= 30A, fSW= 300kHz

OUT

Normalized Module Power Loss

0.90

4.50 4.75 5.00 5.25 5.50

Driver Supply Voltage, V

DRV

and V

CIN

(V)

2.2

I

= 30A, fSW= 300kHz

OUT

2.0

1.8

1.6

1.4

1.2

1.0

0.8

Normalized Module Power Loss

0.6

0.6 1.0 1.4 1 .8 2.2 2.6 3.0 3.4

Output Volt age, V

OUT

(V)

Figure 10. Pow er Loss vs. Driver Supply Voltage Figure 11. Pow er Loss vs. Output Voltage

Typical Performance Characteristics (Continued)

Test Conditions: V

=12V, V

IN

unless otherwise specified.

1.06

1.05

1.04

1.03

1.02

1.01

1.00

0.99

Normalized Module Power Loss

0.98 225 275 325 375 425

Output Inductance, L

Figure 12. Power Loss vs. Output Inductance Figure 13. Driver Supply Current vs. Frequency

=1.0V, V

OUT

I

= 30A, fSW= 300kHz

OUT

=5V, V

CIN

(nH)

DRV

=5V, L

=320nH, TA=25°C, and natural convection cooling;

OUT

50

I

= 0A

OUT

45

(mA)

40

VCIN

+ I

35

VDRV

30 25 20 15 10

Driver Supply Current, I

5

200 300 400 500 600 700 800 900 10 00

Module Sw itching Freq uenc y , fSW(kHz)

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

17

I

= 0A, fSW= 300kHz

(mA)

VCIN

OUT

16

+ I

15

VDRV

, I

14

13

Driver Supp ly Cur ren t

12

4.50 4.75 5.00 5.25 5.50

Driver Supply Voltage, V

DRV

and V

CIN

(V)

Figure 14. Driver Supply Current vs. Driver

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

Norma lize d D riv e r Supply Curre nt

0.94 0 5 10 15 20 25 30 35 40 45

300kHz

1MHz

Module Output Curre nt, I

OUT

(A)

Figure 15. Driver Supply Current vs. Output Current

Supply Voltage

4.0 TA= 25°C

3.5

3.0

2.5

2.0

1.5

1.0

PWM Threshold Voltage (V)

0.5

4.50 4.75 5.00 5.25 5.50

V

IH_PWM

V

TRI_HI

V

HIZ_PWM

V

TRI_LO

V

IL_PWM

Driver Supply Voltage, V

DRV

& V

CIN

(V)

4.0

V

= 5V

CIN

3.5

V

3.0

2.5

2.0

1.5

PWM Threshold Voltage ( V)

1.0

0.5

-50 -25 0 25 50 75 100 12 5 150

Driver IC Junction Temperature, TJ(°C)

TRI_HI

V

IH_PWM

V

TRI_LO

V

IL_PWM

Figure 16. PWM Thresholds vs. Driver Supply Voltage Figure 17. PWM Thresholds vs. Temperature

Typical Performance Characteristics (Continued)

Test Conditions: V

=12V, V

IN

unless otherwise specified.

2.2

TA=

25°C

2.0

V

1.8

IH_SMOD

=1.0V, V

OUT

=5V, V

CIN

DRV

=5V, L

OUT

2.0

1.9

1.8

1.7

=320nH, TA=25°C, and natural convection cooling;

V

= 5V

CIN

V

IH_SMOD

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

1.6

V

1.4

IL_SMOD

SMOD# Threshold Voltage (V)

1.2

4.50 4.75 5.00 5.25 5.50

Drive r Supply Voltag e, V

CIN

(V)

Figure 18. SMOD# Thresholds vs. Driver

Supply Voltage

-9.0

V

= 5V

CIN

(uA)

-9.5

PLU

-10.0

-10.5

-11.0

-11.5

SMOD# Pull- up Cur r e n t, I

-12.0

-50 -25 0 25 50 75 100 125 150

Driver IC Junction Temperature, TJ(oC)

1.6

1.5

SMOD Thre s hold Voltage (V)

1.4

1.3

-50 -25 0 25 50 75 100 125 150

V

IL_SMOD

Driver IC Jun ct ion Temperature (oC)

Figure 19. SMOD# Thresholds vs. Temperature

2.00

V

= 5V

CIN

1.90

1.80

1.70

1.60

1.50

DISB Thr e s hold Voltage (V)

1.40

-50 -25 0 25 50 75 100 125 150

Driver IC Junct i on Temperature, TJ(°C)

V

IH_DISB

V

IL_DISB

Figure 20. SMOD# Pull-Up Current vs. Temperature Figure 21. Disable Thresholds vs. Driver

Supply Voltage

2.1

TA= 25oC

2.0

1.9

1.8

1.7

1.6

1.5

1.4

DISB# Thre s hold Volta ge (V)

1.3

4.50 4.75 5 .00 5.25 5.50

Driver Supply Voltage, V

V

IH_DISB

V

IL_DISB

CIN

(V)

12.0

V

= 5V

11.5

(µA)

PLD

11.0

10.5

10.0

9.5

9.0

8.5

DISB # Pull-Down Current , I

8.0

CIN

-50 -25 02550 75 100 125 150

Driver IC Junction Temperature (

o

C)

Figure 22. Disable Thresholds vs. Temperature Figure 23. Disable Pull-Down Current

vs. Temperature

A

p

Functional Description

The FDMF6707C is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz.

VCIN and Disable (DISB#)

The VCIN pin is monitored by an under-voltage lockout (UVLO) circuit. When V is enabled. When V disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < V holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > V

Table 1. UVLO and Disable Logic

UVLO DISB# Driver State

0 X Disabled (GH, GL=0)

1 0 Disabled (GH, GL=0)

1 1 Enabled (See Table 2)

1 Open Disabled (GH, GL=0)

Note:

3. DISB# internal pull-down current source is 10µA.

Thermal Warning Flag (THWN#)

The FDMF6707C provides a thermal warning flag (THWN#) to advise of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to highimpedance state once the temperature falls to the reset temperature (135°C). The THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module.

HIGH

THWN# Logic State

Normal Operation

LOW

Figure 24. THWN Operation

rises above ~3.1V, the driver

CIN

falls below ~2.7V, the driver is

CIN

), which

IL_DISB

).

IH_DISB

135°C Reset Temperature

150°C

ctivation

Tem

erature

Thermal Warning

T

J_driver IC

Three-State PWM Input

The FDMF6707C incorporates a three-state 5V PWM input gate drive design. The three-state gate drive has both logic HIGH level and LOW level, along with a three-state shutdown window. When the PWM input signal enters and remains within the three -state window for a defined hold-off time (t

D_HOLD-OFF

), both GL and GH are pulled LOW. This feature enables the gate drive to shut down both high-and low-side MOSFETs to support features such as phase shedding, a common feature on multi-phase voltage regulators.

Exiting Three-State Condition

When exiting a valid three-state condition, the FDMF6707C design follows the PWM input command. If the PWM input goes from three-state to LOW, the lowside MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on, as illustrated in Figure 25. The FDMF6707C design allows for short propagation delays when exiting the

three-state window (see Electrical Characteristics).

Low-Side Driver

The low-side driver (GL) is designed to drive a groundreferenced low R

N-channel MOSFET. The bias

DS(ON)

for GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW.

High-Side Driver

The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (C held at PGND, allowing C

). During startup, V

BOOT

to charge to V

BOOT

through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from C As Q1 turns on, V pin to V

+ V

IN

and delivered to the gate of Q1.

BOOT

rises to VIN, forcing the BOOT

SWH

, which provides sufficient VGS

BOOT

enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to V recharged to V

when V

DRV

SWH

. C

BOOT

is then

falls to PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, t

D_HOLD-OFF

SWH

is

DRV

.

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Adaptive Gate Drive Circuit

_

V

The driver IC design ensures minimum MOSFET dead time, while eliminating potential shoot-through (crossconduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to prevent simultaneous conduction. Figure 25 provides the timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 turns off after a propagation delay (t

PD_PHGLL

~1V, Q1 turns on after adaptive delay, t

). Once the GL pin is discharged below

D_DEADON

.

To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 turns off after a propagation delay (t

PD_PLGHL

Once the VSWH pin falls below ~2.2V, Q2 turns on after adaptive delay, t monitored. When V

D_DEADOFF

GS(Q1)

. Additionally, V

GS(Q1)

is discharged below ~1.2V, a secondary adaptive delay is initiated that results in Q2 being driven on after t

D_TIMEOUT

state. This function ensures C

, regardless of VSWH

is recharged each

BOOT

switching cycle in the event that the VSWH voltage does not fall below the 2.2V adaptive threshold. Secondary delay t

D_TIMEOUT

is longer than t

D_DEADOFF

.

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

).

is

V

PWM

GH

to

VSWH

GL

IH_PWM

CCM

t

PD_PHGLL

90%

1.0V

t

D_DEADON

V

IL_PWM

less than

t

-

OFF

D_HOLD -

t

D_HOLD

2.2

10%

t

PD

PLGHL

t

D_DEADOFF

t

R_GL

Enter

3 -

OFF

DCM

t

F_GL

State

V

IH_PWM

t

R_GH

t

Exit

3-State

PD_TSGHH

t

D_HOLD -OFF

Notes:

= propagation delay from external sign al (PWM, SMOD#, etc.) to IC generated signal. Example (t

t

PD_xxx

t

= delay from IC generated signal to IC generated signal. Example (t

D_xxx

PWM Exiting 3-state

= PWM rise to LS VGS fall, V

t

PD_PHGLL

t

= PWM fall to HS VGS fall, V

PD_PLGHL

t

= PWM rise to HS VGS rise, V

PD_PHGHH

SMOD# Dead Times

= SMOD# fall to LS VGS fall, V

t

PD_SLGLL

t

= SMOD# rise to LS VGS rise, V

PD_SHGLH

to 90% LS VGS t

IH_PWM

to 90% HS VGS t

IL_PWM

to 10% HS VGS (SMOD# held LOW)

IH_PWM

to 90% LS VGS t

IL_SMOD

to 10% LS VGS t

IH_SMOD

– LS VGS (GL) LOW to HS VGS (GH) HIGH)

D_DEADON

PD_TSGHH

PD_TSGLH

D_DEADON

D_DEADOFF

V

TRI_HI

t

F_GH

IH_PWM

DCM

t

PD_TSGHH

Enter

3

-State

PD_PHGLL

= PWM 3-state to HIGH to HS VGS rise, V

= PWM 3-state to LOW to LS VGS rise, V

= LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS

= VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS

Exit 3 S t at e

– PWM going HIGH to LS VGS (GL) going LOW)

less than

t

D_HOLD -

IH_PWM

IL_PWM

t

D_HOLD

OFF

Enter

3 -

to 10% HS VGS

to 10% LS VGS

State

-OFF

t

PD_TSGLH

Exit

State

3-

V

TRI_HI

TRI_LO

IL_PWM

90%

10%

V

90%

1

IN

OUT

0%

Figure 25. PWM and 3-StateTiming Diagram

Skip Mode (SMOD)

V

#

The SMOD function allows higher converter efficiency under light-load conditions. During SMOD, the low-side FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow – also known as Diode Emulation Mode.

When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode allows for gating on the low-side FET. When the SMOD# pin is pulled LOW, the low-side FET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD when the controller detects light-load condition from output current sensing. This pin is active LOW.

See Figure 26 for timing delays.

SMOD

Table 2. SMOD Logic

DISB# PWM SMOD# GH GL

0 X X 0 0

1 3-State X 0 0

1 0 0 0 0

1 1 0 1 0

1 0 1 0 1

1 1 1 1 0

Note:

4. The SMOD feature is intended to have low

propagation delay between the SMOD signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis.

V

IL_SMOD

IH_SMOD

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

V

IH_PWM

CCM

t

PD_PHGHH

LOW

GS

HS turn -on with SMOD# LOW

10%

DCM

t

Delay from SMOD# going

HIGH to LS VGSHIGH

PD_SHGLH

10%

V

OUT

PWM

GH

to

SWH

V

SWH

GL

IH_PWM

t

PD_PHGLL

t

D_DEADON

90%

1.0V

t

PD_PLGHL

V

IL_PWM

90%

10%

2.2V

t

D_DEADOFF

10%

CCM

t

PD_SLGLL

Delay from SMOD# going

LOW to LS V

Figure 26. SMOD Timing Diagram

Application Information

A

V

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Supply Capacitor Selection

For the supply inputs (V bypass capacitor is required to reduce noise and to supply peak transient currents during gate drive switching action. It is recommended to use a minimum capacitor value of 1µF X7R or X5R. Keep this capacitor close to the VCIN and VDRV pins and connect it to the GND plane with vias.

DRV

and V

), a local ceramic

CIN

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C

), as shown in Figure 27. A bootstrap capacitance

BOOT

of 100nF X7R or X5R capacitor is typically adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating near the maximum rated V high-side MOSFET turn-on slew rate and V overshoot. Typical R effective in reducing V

and is effective at controlling the

IN

values from 0.5Ω to 2.0Ω are

BOOT

overshoot.

SWH

V

5

I

5

C

VDR

R

CIN

SHW

C

CIN

VCIN Filter

The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFETs. In most cases, VDRV can be connected directly to VCIN, which supplies power to the logic circuitry of the gate driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values would be 10Ω (R (C

) from VCIN to CGND (see Figure 27).

VCIN

) placed between VDRV and VCIN and 1µF

VCIN

Power Loss and Efficiency

Measurement and Calculation

Refer to Figure 28 for power loss testing method. Power loss calculations are:

P

=(VIN x IIN) + (V5V x I5V) (W)

IN

x I

P

SW=VSW

P

OUT=VOUT

P

LOSS_MODULE=PIN

P

LOSS_BOARD=PIN

EFF

MODULE

EFF

BOARD

C

VIN

(W)

OUT

x I

(W)

OUT

- PSW (W)

- P

(W)

OUT

=100 x PSW/PIN (%)

=100 x P

I

IN

V

IN

OUT/PIN

(%)

(1) (2) (3) (4) (5) (6) (7)

DISB

PWM Input

OFF

ON

Open -

Drain

Output

DISB

PWM

Input

OFF

Open -

Drain

Output

VCIN

VDRV

DISB

PWM

SMOD#

THWN#

CGND

Figure 27. Block Diagram With V

V

5V

ON

I

5

C

VDRV

DISB

PWM

SMOD#

THWN#

FDMF6707C

PGN

VCIN

VDRV

FDMF6707C

FDM 67 5

CGND

VIN

R

BOOT

VSWH

PHASE

VIN

BOOT

VSWH

PHASE

PGN

R

C

BOOT

VIN

C

V V

I

IN

V V

BOOT

C

SW

BOOT

SW

CIN

L

OUT

Filter

V

IN

L

OUT

I

OUT

V

OUT

C

OUT

I

OUT

C

OUT

Figure 28. Power Loss Measurement

PCB Layout Guidelines

Figure 29 provides an example of a proper layout for the FDMF6707C and critical components. All of the highcurrent paths, such as V

IN

, V

SWH

, V

OUT

, and GND copper, should be short and wide for low inductance and resistance. This technique achieves a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance.

The following guidelines are recommendations for the PCB designer:

1. Input ceramic bypass capacitors must be placed

close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation.

2. The V

copper trace serves two purposes. In

SWH

addition to being the high-frequency current path from the DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor to minimize losses and temperature rise. Note that the VSWH node is a high-voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for the lower FET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission.

3. An output inductor should be located close to the

FDMF6707C to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS.

4. PowerTrench

®

MOSFETs are used in the output stage. The power MOSFETs are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The resistor and capacitor need to be of proper size for the power dissipation.

5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN to CGND, VDRV to CGND, and BOOT to PHASE pins to ensure clean and stable power. Routing width and length should be considered.

6. Include a trace from PHASE to VSWH to improve noise margin. Keep the trace as short as possible.

7. The layout should include a placeholder to insert a small-value series boot resistor (R

) between the

BOOT

boot capacitor (C BOOT-to-VSWH loop size, including R C

BOOT

resistor may be required when operating near the maximum rated VIN. The boot resistor is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. R operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing. However, inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. R typically effective in reducing VSWH overshoot.

The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is

discouraged

power path. Added inductance in series with the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing.

8. CGND pad and PGND pins should be connected to the GND plane copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs.

9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to PGND capacitor: this may lead to excess current flow through the BOOT diode.

10. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary.

11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical high-frequency components, such as R capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they should be connected from the backside through a network of low-inductance vias.

) and DrMOS BOOT pin. The

BOOT

and

, should be as small as possible. The boot

can improve noise

BOOT

values from 0.5Ω to 2.0Ω are

BOOT

since this adds inductance to the

, C

BOOT

, the RC snubber, and bypass

BOOT

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Top View Bottom View

Figure 29. PCB Layout Example

Physical Dimensions

0.10 C

2X

6.00

B

A

6.00

PIN#1 INDICATOR

2.50

31

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

5.80

4.50

2130

20

0.40

0.65

11

0.35

0.50 (0.70)

0.40

2.00±0.10

0.10

0.08 C

0.40

C

FRONT VIEW

(2.20)

21

20

11

10

(0.20)

BOTTOM VIEW

1.10

0.90

0.30

0.20

TOP VIEW

4.40±0.10

0.05

0.00

DETAIL 'A'

SCALE: 2:1

(0.20)

0.10 C

2X

SEE DETAIL 'A'

0.10 CAB

0.05

0.30 (40X)

0.20

30

31

2.40±0.10

1.50±0.10

40

1

2.00±0.10

0.50

C

SEATING

PLANE

0.25

1.60

40

0.60

0.50 TYP

C

0.20

0.50

0.30

NOTES: UNLESS OTHERWISE SPECIFIED

A) DOES NOT FULLY CONFORM TO JEDEC

REGISTRATION MO-220, DATED

B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV2

1

2.10

LAND PATTERN

RECOMMENDATION

PIN #1 INDICATOR

(40X)

MAY/2005.

10

0.15

2.10

Figure 30. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module

Datasheet FDMF6707C Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual