Fairchild FDG6318P service manual
January 2003
FDG6318P
Dual P-Channel, Digital FET
FDG6318P
General Description
These dual P-Channel logic level enhancement mode
MOSFET are produced using Fairchild Semiconductor’s
advanced PowerTrench process that has been
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for bipolar digital
transistors and small signal MOSFETS.
Applications
• Battery management
Features
• –0.5 A, –20 V. R
R
• Very low level gate drive requirements allowing direct
operation in 3V circuits (V
• Compact industry standard SC70-6 surface mount
package
= 780 mΩ @ VGS = –4.5 V
DS(ON)
= 1200 mΩ @ VGS = –2.5 V
DS(ON)
< 1.5V).
GS(th)
S
G
D
S
G
1 or 4
2 or 5
6 or 3
5 or 2
D
G
D
Pin 1
G
S
SC70-6
The pinouts are symmetrical; pin 1 and pin 4 are interchangeable.
Absolute Maximum Ratings
TA=25oC unless otherwise noted
3 or 6
D
4 or 1
S
Symbol Parameter Ratings Units
V
Drain-Source Voltage –20 V
DSS
V
Gate-Source Voltage ±12 V
GSS
ID Drain Current – Continuous
– Pulsed –1.8
PD Power Dissipation for Single Operation
TJ, T
Operating and Storage Junction Temperature Range –55 to +150
STG
(Note 1)
–0.5 A
(Note 1)
0.3 W
°C
Thermal Characteristics
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1)
415
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
2003 Fairchild Semiconductor Corporation
.38 FDG6318P 7’’ 8mm 3000 units
°C/W
FDG6318P Rev C (W)
FDG6318P
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown
DSS
Voltage
∆BV
DSS
∆T
J
I
Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1
DSS
I
Gate–Body Leakage
GSS
On Characteristics
V
GS(th)
∆V
GS(th)
∆TJ
R
DS(on)
Breakdown Voltage Temperature
Coefficient
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
I
On–State Drain Current VGS = –4.5 V, VDS = –5 V –1.8 A
D(on)
V
= 0 V, ID = –250 µA
GS
= –250 µA, Referenced to 25°C
I
D
V
= ±12 V, VDS = 0 V
GS
V
= VGS, ID = –250 µA
DS
= –250 µA, Referenced to 25°C
I
D
VGS = –4.5 V, ID = –0.5 A
V
= –2.5 V, ID = –0.4 A
GS
= –4.5 V, ID = –0.5 A, TJ=125°C
V
GS
–20 V
–10
mV/°C
µA
±100
nA
–0.65 –1.2 –1.5 V
2
580
980
1200
780
780
mV/°C
mΩ
gFS Forward Transconductance VDS = –5 V, ID = –0.5 A 1.1 S
Dynamic Characteristics
C
Input Capacitance 83 pF
iss
C
Output Capacitance 20 pF
oss
C
Reverse Transfer Capacitance
rss
RG Gate Resistance
Switching Characteristics
t
Turn–On Delay Time 6 12 ns
d(on)
(Note 2)
tr Turn–On Rise Time 12 22 ns
t
Turn–Off Delay Time 6 13 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 0.86 1.2 nC
Qgs Gate–Source Charge 0.22 nC
Qgd Gate–Drain Charge
= –10 V, V
V
DS
GS
f = 1.0 MHz
V
= 15 mV, f = 1.0 MHz
GS
V
= –10 V, ID = 1 A,
DD
= –4.5 V, R
V
GS
V
= –10 V, ID = –0.6 A,
DS
= –4.5 V
V
GS
GEN
= 0 V,
= 6 Ω
11 pF
12.1
Ω
1 3 ns
0.25 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current –0.25 A
VSD Drain–Source Diode Forward
Voltage
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
is guaranteed by design while R
θJC
VGS = 0 V, IS = –0.25 A
I
= –0.5 A,
F
= 100 A/µs
d
iF/dt
is determined by the user's board design. R
θJA
(Note 2)
–0.83 –1.2 V
12.6
2.52
= 415°C/W when mounted on a minimum pad .
θJA
FDG6318P Rev C (W)
ns
nC
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