Fairchild FAN5365 service manual

August 2011

FAN5365 1A / 0.8A, 6MHz Digitally Programmable Regulator

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

Features

 High Efficiency (>88%) at 6MHz  800mA or 1A Output Current  Regulation Maintained with V  6-Bit V

Programmable from 0.75 to 1.975V

OUT

from 2.3V to 5.5V

IN

 6MHz Fixed-Frequency Operation (PWM Mode)  Excellent Load and Line Transient Response  Small Size, 470nH Inductor Solution  ±2% DC Voltage Accuracy in PWM Mode  25ns Minimum On-Time  High-Efficiency, Low-Ripple, Light-Load PFM  Smooth Transition between PWM and PFM  40A Operating PFM Quiescent Current

2

 I

C™-Compatible Interface up to 3.4Mbps

 Pin-Selectable or I

2C™

Programmable Output Voltage

 9-Bump, 1.27 x 1.29mm, 0.4mm Pitch WLCSP Package

Applications

 3G, WiFi  Netbooks

®

, WiMAX™, and WiBro® Data Cards

®

, Ultra-Mobile PCs

 SmartReflex™-Compliant Power Supply  Split Supply DSPs and P Solutions OMAP™, XSCALE™  Handset Graphic Processors (NVIDIA

®

, ATI)

Description

The FAN5365 is a high-frequency, ultra-fast transient response, synchronous step-down, DC-DC converter optimized for low-power applications using small, low-cost inductors and capacitors. The FAN5365 supports up to 800mA or 1A load current.

The FAN5365 is ideal for mobile phones and similar portable applications powered by a single-cell Lithium-Ion battery. With an output voltage range adjustable via I from 0.75V to 1.975V, it supports low-voltage DSPs and processors, core power supplies, and memory modules in smart phones, data cards, and hand-held computers.

The FAN5365 operates at 6MHz (nominal) fixed switching frequency in PWM mode.

During light-load conditions, the regulator includes a PFM mode to enhance light-load efficiency. The regulator transitions smoothly between PWM and PFM modes with no glitches on V consumption is reduced to less than 200nA.

The serial interface is compatible with fast / standard mode, fast mode plus, and high-speed mode I allowing transfers up to 3.4Mbps. This interface is used for dynamic voltage scaling with 12.5mV voltage steps, for reprogramming the mode of operation (PFM or forced PWM), or to disable/enable the output voltage.

The chip's advanced protection features include short-circuit protection and current and temperature limits. During a sustained over-current event, the IC shuts down and restarts after a delay to reduce average power dissipation into a fault.

During startup, the IC controls the output slew rate to minimize input current and output overshoot at the end of soft-start. The IC maintains a consistent soft-start ramp, regardless of output load during startup.

The FAN5365 is available in a 1.27 x 1.29mm, 9-bump WLCSP package.

. In hardware shutdown, the current

OUT

2

C™ interface

2

C specifications,

All trademarks are the property of their respective owners

Ordering Information

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

Part Number

(1)

Option

Slave Address LSB

Output

Current

V

Programming

OUT

Power-up

Defaults

A2 A1 A0 mA Min. Max. VSEL0 VSEL1

1.4375

(3)

1.05 1.20 WLCSP-09

)

(3

0.95 1.10

listed.

OUT

FAN5365UC00X 00 0 1 0 800 0.7500 1.4375

FAN5365UC02X

FAN5365UC03X

FAN5355UC06X

02 1 1 0 800 0.7500

(2)

03 0 0 0 1000 0.7500 1.5375 1.00 1.20 WLCSP-09

(2)

06 0 0 0 1000 1.1875 1.9750 1.80 1.80 WLCSP-09

Notes:

1. The “X” designator on the part number indicates tape and reel packaging.

2. Preliminary; not full production release at this time. Contact a Fairchild representative for information.

3. V

is limited to the maximum voltage for all VSEL codes greater than the maximum V

OUT

Typical Application

EN

VSEL

SDA

SCL

MODULATOR

Q1

Q2

VIN

SW

L

PGND

VIN

C

IN

VOUT

C

OUT

Package

WLCSP-09

AGND

VOUT

Figure 1. Typical Application

Table 1. Recommended External Components

Component Description Vendor Parameter Min. Typ. Max. Units

(4)

390 470 600 nH

L (L

) 470nH Nominal Murata, TDK, FDK

OUT

(5)

C

OUT

CIN

0603 (1.6x0.8x0.8), 10F X5R

0402 (1x0.5x0.25), 4.7F X5R

Various C

Taiyo-Yuden 1.6 4.7

Notes:

4. Minimum L incorporates tolerance, temperature, and partial saturation effects (L decreases when increasing current).

5. A capacitor similar to CIN can be used for C

. With 1.4V of bias, a 4.7F 0402 capacitor minimum value is 2.5F.

OUT

The regulator is stable, but transient response degraded due to large signal effects.

6. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to frequency, dielectric, and voltage bias effects. C

is biased with a higher voltage which reduces its effective capacitance

IN

by a larger amount.

L

DCR (Series R) 80

(6)

2.2 10.0 15.0

m

F

Pin Configuration

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

A1 A2

B1

C1

B2

C2

A3

B3

C3

Bumps Facing Down

Figure 2. WLCSP-09, 0.4mm Pitch

Pin Definitions

Pin # Name Description

A1 VSEL

A2

A3

B1

B2

B3

C1

VIN

SDA

SW

SCL

EN

VOUT

C2 PGND

C3

AGND

Voltage Select. When HIGH, V can be overridden through I

Input Voltage. Connect to input power source. The connection from this pin to C possible.

SDA. I

Switching Node. Connect to output inductor.

SCL. I

Enable. When this pin is HIGH, the circuit is enabled. When LOW, part enters shutdown mode and

input current is minimized. This pin should not be left floating.

Output Voltage Monitor. Tie this pin to the output voltage at C control circuit and does not carry DC current.

Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The connection from this pin to the bottom of C

Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. AGND should be connected to PGND at a single point.

2

C interface serial data. This pin should not be left floating.

2

C interface serial clock. This pin should not be left floating.

is set by VSEL1. When LOW, V

OUT

2

C register settings. This pin should not be left floating.

should be as short as possible.

IN

A3 A2

B3

C3

B2

C2

A1

B1

C1

Bumps Facing Up

is set by VSEL0. This behavior

OUT

should be as short as

IN

. This is a signal input pin to the

OUT

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Units

VIN, SW Pins –0.3 6.5

VCC

ESD Electrostatic Discharge Protection

–0.3 2.5

OUT

Other Pins –0.3 VIN + 0.3

Human Body Model, JESD22-A114 3

Charged Device Model, JESD22-C101 1

(7)

TJ Junction Temperature –40 +150 °C

T

Storage Temperature –65 +150 °C

STG

TL Lead Soldering Temperature, 10 Seconds +260 °C

Note:

7. Lesser of 6.5V or VCC+0.3V.

V V

KV

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Min. Max. Units

VIN Supply Voltage 2.3 5.5 V

V

SDA and SCL Voltage Swing

CCIO

TA Ambient Temperature –40 +85 °C

TJ Junction Temperature –40 +125 °C

Note:

8. The I2C interface operates with t swings greater than 2.5V are required (for example, if the I increased to 80ns. Most I provides ample t

HD;DAT

2

C masters change SDA near the midpoint between the falling and rising edges of SCL, which

.

(8)

1.2 2.0 V

= 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage

HD;DAT

2

C bus is pulled up to VIN), the minimum t

HD;DAT

must be

(9)

Dissipation Ratings

Package R

Wafer-Level Chip-Scale Package (WLCSP) 110ºC/W 900mW 9mW/ºC

Notes:

9. Maximum power dissipation is a function of T allowable ambient temperature is P

10. This thermal data is measured with a high-K board (four-layer board, according to the JESD51-7 JEDEC standard).

= [T

D

J(max)

(10

)

θJA

, θJA, and TA. The maximum allowable power dissipation at any

J(max)

Power Rating

at T

≤ 25°C

A

- TA ] / θJA.

Derating Factor

> TA = 25ºC

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

Electrical Specifications

Unless otherwise noted, over the recommended operating range for VIN and TA, EN = VSEL = SCL = SDA = 1.8V, and register VSEL0[6] bit = 1. Typical values are at V

Symbol Parameter Conditions Min. Typ. Max. Units

Power Supplies

IQ Quiescent Current

ISD Shutdown Supply Current

V

Under-Voltage Lockout Threshold

UVLO

V

ENABLE, VSEL, SDA, SCL

Power Switch and Protection

R

Frequency Control

Output Regulation

Under-Voltage Lockout Hysteresis 160 mV

UVHYST

VIH HIGH-Level Input Voltage 1.05 V VIL LOW-Level Input Voltage 0.4 V

IIN Input Bias Current Input Tied to GND or VIN 0.01 1.00

P-Channel MOSFET On

DS(ON)P

I

LKGP

DS(ON)N

I

LKGN

I

LIMPK

T

V



IV



V

RIPPLE

Resistance

P-Channel Leakage Current VDS = 5.5V 0.2 1.0

N-Channel MOSFET On Resistance

N-Channel Leakage Current VDS = 5.5V 0.3 1.0

P-MOS Current Limit

Thermal Shutdown 150 °C

LIMIT

Thermal Shutdown Hysteresis 20 °C

HYST

fSW Switching Frequency

OUT

LOAD

OUT

VV

IN

V

Accuracy

OUT

Load Regulation I

Line Regulation

(11)

PWM Operation 5.4 6.0 6.6 MHz

Output Ripple Voltage

= 3.6V, TA = 25°C. Circuit and components according to Figure 1.

IN

I

= 0mA, PFM Mode, 2.3V<=VIN<=4.5V 40 55

O

IO = 0mA, PFM Mode, 2.3V<=VIN<=5.5V 40 65 IO = 0mA, 6MHz PWM Mode 6.3 mA

EN = GND 0.1 1.0

EN = VIN, EN_DCDC bit = 0, SDA = SCL = 1.8V (Software Shutdown)

Rising 2.18 2.25 V

V

IN

N/A N/A

VIN Falling 1.95 2.02 V

VIN = 3.6V 300 mΩ

VIN = 3.6V 200 mΩ

Options 00, 02 1150 1350 1600 Options 03, 06 1300 1550 1840

I

= 0, Forced PWM, V

OUT(DC)

Default Value

2.3V ≤ VIN ≤ 5.5V, V Maximum, I

= 0 to 1A, Forced PWM

OUT(DC)

2.3V ≤ VIN ≤ 5.5V, V Maximum, I

= 0 to 1A, Auto

OUT(DC)

from Minimum to

OUT

from Minimum to

OUT

= VSEL1

OUT

–1.5 1.5 %

–2.0 2.0 %

–2.0 3.5 %

PWM/PFM

= 0 to 1A, Forced PWM –0.2 %/A

OUT(DC)

2.3V ≤ V Forced PWM

PWM Mode, V PFM Mode, I

≤ 5.5V, I

IN

OUT(DC)

= 300mA,

OUT(DC)

= 1.2V 4 mV

OUT

0 %/V

= 10mA 16 mV

Continued on the following page…

A

A

mA

P-P

Electrical Specifications (Continued)

Unless otherwise noted, over the recommended operating range for V VSEL0[6] bit = 1. Typical values are at V

= 3.6V, TA = 25°C. Circuit and components according to Figure 1.

IN

Symbol Parameter Conditions Min. Typ. Max. Units

DAC

Resolution 6 Bits

Differential Nonlinearity Monotonicity Assured by Design 0.8 LSB

Timing

I2CEN EN HIGH to I2C Start 250

t

V(L-H)

V

LOW to HIGH Settling

OUT

Soft-Start

tSS Regulator Enable to Regulated V

Notes:

11. Limited by the effect of t

minimum (see Figure 14 in Typical Performance Characteristics).

OFF

Transition from 0.75V to 1.438V V

Settled to within 2% of Setpoint

OUT

R

LOAD

> 5, to V

and TA, EN = VSEL = SCL = SDA = 1.8V, and register

IN

7

= Power-up Default

OUT

140 180

s

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

Block Diagram

EN

VSEL

INTERFACE

SDA

SCL

AND LOGIC

6 Mhz Osc

I2C

DAC

REF

SOFT START

FPWM

EN_REG

CLK

Figure 3 Block Diagram

MODULATOR

Q1

Q2

VIN

SW

PGND

VOUT

AGND

VIN

C

IN

VOUT

L

C

OUT

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

I2C Timing Specifications

Guaranteed by design.

Symbol Parameter Conditions Min. Typ. Max. Units

Standard Mode 100 Fast Mode 400

f

SCL Clock Frequency

SCL

t

BUF

t

HD;STA

t

LOW

t

HIGH

t

SU;STA

t

SU;DAT

t

HD;DAT

t

RCL

Bus-free Time between STOP and START Conditions

START or Repeated START Hold Time

SCL LOW Period

SCL HIGH Period

Repeated START Setup Time

Data Setup Time

Data Hold Time

SCL Rise Time

Fast Mode Plus 1000 High-Speed Mode, CB < 100pF 3400 High-Speed Mode, CB < 400pF 1700 Standard Mode 4.7 Fast Mode 1.3 Fast Mode Plus 0.5 Standard Mode 4 Fast Mode 600 ns Fast Mode Plus 260 ns High-Speed Mode 160 ns Standard Mode 4.7

Fast Mode 1.3

Fast Mode Plus 0.5 High-Speed Mode, CB < 100pF 160.0 ns High-Speed Mode, CB < 400pF 320.0 ns Standard Mode 4 Fast Mode 600 ns Fast Mode Plus 260 ns High-Speed Mode, CB < 100pF 60 ns High-Speed Mode, CB < 400pF 120 ns Standard Mode 4.7 Fast Mode 600.0 ns Fast Mode Plus 260.0 ns High-Speed Mode 160.0 ns Standard Mode 250 Fast Mode 100 Fast Mode Plus 50 High-Speed Mode 10 Standard Mode 0 3.45

(8)

Fast Mode 0 900.00 ns Fast Mode Plus 0 450.00 ns High-Speed Mode, CB < 100pF 0 70.00 ns High-Speed Mode, CB < 400pF 0 150.00 ns Standard Mode 20+0.1C

1000

B

Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB < 100pF 10 80 High-Speed Mode, CB < 400pF 20 160

Continued on the following page…

kHz

s

ns

s

ns

FAN5365 — 1A / 0.8A, 6MHz Digitally Programmable Regulator

I2C Timing Specifications (Continued)

Guaranteed by design.

Symbol Parameter Conditions Min. Typ. Max. Units

Standard Mode 20+0.1C Fast Mode 20+0.1CB 300

t

SCL Fall Time

FCL

Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB < 100pF 10 40 High-Speed Mode, CB < 400pF 20 80

t

RCL1

Rise Time of SCL after a Repeated START Condition and after ACK Bit

High-Speed Mode, C High-Speed Mode, CB < 400pF 20 160

< 100pF 10 80

B

Standard Mode 20+0.1C Fast Mode 20+0.1CB 300

t

SDA Rise Time

RDA

Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB < 100pF 10 80 High-Speed Mode, CB < 400pF 20 160 Standard Mode 20+0.1C Fast Mode 20+0.1CB 300

t

SDA Fall Time

FDA

Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB < 100pF 10 80 High-Speed Mode, CB < 400pF 20 160 Standard Mode 4

t

Stop Condition Setup Time

SU;STO

Fast Mode 600 ns Fast Mode Plus 120 ns High-Speed Mode 160 ns

CB Capacitive Load for SDA and SCL 400 pF

300

B

1000

B

300

B

ns

s