Fairchild FAN5026 service manual

FAN5026

FAN5026 — Dual DDR / Dual-Output PWM Controller

March 2011

Dual DDR / Dual-Output PWM Controller

Features



Highly Flexible, Dual Synchronous Switching PWM Controller that Includes Modes for:

-

DDR Mode with In-phase Operation for Reduced Channel Interference

-

90° Phase-shifted, Two-stage DDR Mode for Reduced Input Ripple

-

Dual Independent Regulators, 180° Phase Shifted



Complete DDR Memory Power Solution

-

V

Tracks V

TT

-

V

Buffered Reference Output

DDQ/2



Lossless Current Sensing on Low-Side MOSFET or Precision Over-Current Using Sense Resistor



VCC Under-Voltage Lockout



Wide Input Range: 3V to 16V



Excellent Dynamic Response with Voltage Feedforward and Average Current-Mode Control



Power-Good Signal



Supports DDR-II and HSTL



28-Lead Thin-Shrink Small-Outline Package

DDQ/2

Applications



DDR V



PC Dual Power Supply



Server DDR Power



Desktop Computer



Graphics Cards

and VTT Voltage Generation

DDQ

Description

The FAN5026 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range of 0.9V to 5.5V required to power I/O, chip-sets, and memory banks in high-performance computers, set-top boxes, and VGA cards. Synchronous rectification and hysteretic operation at light loads contribute to high efficiency over a wide range of loads. Efficiency is enhanced by using MOSFET R current-sense component.

Feedforward ramp modulation, average-current mode control, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180-degree phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR Mode, one of the channels tracks the output voltage of another channel and provides output current sink and source capability — essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5026 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within ±10% of the set point.

Over-voltage protection prevents the output voltage from exceeding 120% of the set point. Normal operation is automatically restored when over-voltage conditions cease. Under-voltage protection latches the chip off when output drops below 75% of the set value after the soft-start sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current-sensing is required, an external current-sense resistor may be used.

as a

DS(ON)

Related Resources



Application Note — AN-6002 Component Calculations and Simulation Tools

Ordering Information

Operating

Part Number

FAN5026MTCX

Temperature

Package Packing Method

Range

-40 to +85°C 28-Lead Thin-Shrink Small-Outline Package (TSSOP) Tape and Reel

Block Diagrams

FAN5026 — Dual DDR / Dual-Output PWM Controller

Figure 1. Dual-Output Regulator

Figure 2. Typical Application

Pin Configuration

FAN5026 — Dual DDR / Dual-Output PWM Controller

Figure 3. TSSOP-28

Pin Definitions

Pin # Name Description

1 AGND

2 LDRV1

27 LDRV2

3 PGND1

26 PGND2

4 SW1

25 SW 2

5 HDRV1

24 HDRV2

6 BOOT1

23 BOOT2

7 ISNS1

22 ISNS2

8 EN1

21 EN2

Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin

Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET.

Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET.

Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain.

High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET.

BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 4.

Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external sense

resistor for current feedback.

Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a latched fault condition. These are CMOS inputs whose state is indeterminate if left open.

9

20

10 VSEN1

19 VSEN2

GND

Ground

Output Voltage Sense. The feedback from the outputs; used for regulation as well as PG,

under-voltage, and over-voltage protection and monitoring.

Continued on the following page…

Pin Definitions

Pin # Name Description

11 ILIM1

12 SS1

17 SS2

13 DDR

14 VIN

15 PG1

16

18

PG2 /

REF2OUT

ILIM2 /

REF2

28 VCC

Current Limit 1. A resistor from this pin to GND sets the current limit.

Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5mA current source.

DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180 degrees out of phase.

Input Voltage. Normally connected to the battery, providing voltage feedforward to set the

amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V input, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and synchronizes the channels 90° out of phase.

Power-Good Flag. An open-drain output that pulls LOW when V the 0.9V reference.

Power-Good 2. When not in DDR Mode, open-drain output that pulls LOW when the V out of regulation or in a fault condition.

Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the V

reference.

DDQ/2

Current Limit 2. When not in DDR Mode, a resistor from this pin to GND sets the current limit.

Reference for reg #2 when in DDR Mode. Typically set to V

VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when

voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling).

OUT1/2

is outside a ±10% range of

SEN

OUT

.

FAN5026 — Dual DDR / Dual-Output PWM Controller

is

Block Diagram

Figure 4. IC Block Diagram

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC VCC Supply Voltage 6.5 V

VIN VIN Supply Voltage 18 V

BOOT, SW, ISNS, HDRV 24 V

BOOTx to SWx 6.5 V

All Other Pins -0.3 VCC+0.3 V

TJ Junction Temperature -40 +150 ºC

T

Storage Temperature -65 +150 ºC

STG

TL Lead Temperature (Soldering,10 Seconds) +300 ºC

FAN5026 — Dual DDR / Dual-Output PWM Controller

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

VCC VCC Supply Voltage 4.75 5.00 5.25 V

VIN VIN Supply Voltage 16 V

TA Ambient Temperature -40 +85 °C

ΘJA Thermal Resistance, Junction to Ambient 90 °C/W

Electrical Characteristics

Recommended operating conditions, unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

Power Supplies

LDRV, HDRV Open, V

I

VCC

V

Current

CC

Above Regulation Point

Shutdown (EN-0) 30 µA

I

SINK

I

SOURCE

V

Current, Sinking VIN = 15V 10 30 µA

IN

VIN Current, Sourcing VIN = 0V -15 -30 µA

ISD VIN Current, Shutdown 1 µA

V

UVLO Threshold

UVLO

V

UVLO Hysteresis 300 mV

UVLOH

Rising VCC 4.30 4.55 4.75 V

Falling 4.10 4.25 4.45 V

Oscillator

f

Frequency 255 300 345 KHz

osc

VPP Ramp Amplitude

V

Ramp Offset 0.5 V

RAMP

G Ramp / VIN Gain

VIN = 16V 2 V

VIN = 5V 1.25 V

VIN ≤ 3V

1V < VIN < 3V 250 mV/V

Reference and Soft-Start

V

Internal Reference Voltage 0.891 0.900 0.909 V

REF

ISS Soft-Start Current At Startup 5 µA

VSS Soft-Start Complete Threshold 1.5 V

PWM Converters

Load Regulation I

I

SEN

UVLO

V

TSD

Bias Current 50 80 120 nA

SEN

Under-Voltage Shutdown % of Set Point, 2µs Noise Filter 70 75 80 %

from 0 to 5A, VIN from 5 to 15V -2 +2 %

OUTX

UVLO Over-Voltage Threshold % of Set Point, 2µs Noise Filter 115 120 125 %

I

Over-Current Threshold

SNS

R

= 68.5KΩ, Figure 12

ILIM

Minimum Duty Cycle 10 %

Output Drivers

HDRV Output Resistance

LDRV Output Resistance

Sourcing 12 15

Sinking 2.4 4.0

Sourcing 12 15

Sinking 1.2 2.0

Power-Good Output and Control Pins

Lower Threshold % of Set Point, 2µs Noise Filter -86 -94 %

Upper Threshold % of Set Point, 2µs Noise Filter 108 116 %

PG Output Low IPG = 4mA 0.5 V

Leakage Current V

PG2/REF2OUT Voltage

= 5V 1 µA

PULLUP

DDR = 1, 0 mA < I

DDR, EN Inputs

V

Input High 2 V

INH

V

Input Low 0.8 V

INL

SEN

REF2OUT

Forced

≤10mA

2.2 3.0 µA

125 mV/V

112 140 168 µA

Ω

99.00 1.01 V

%

REF2

FAN5026 — Dual DDR / Dual-Output PWM Controller