Fairchild FAN4803 service manual

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FAN4803

8-Pin PFC and PWM Controller Combo

Features

• Internally synchronized PFC and PWM in one 8-pin IC

• Patented one-pin voltage error amplifier with advanced
input current shaping technique

• Peak or average current, continuous boost, leading edge
PFC (Input Current Shaping Technology)

• High efficiency trailing-edge current mode PWM

• Low supply currents; start-up: 150µA typ., operating:
2mA typ.

• Synchronized leading and trailing edge modulation

• Reduces ripple current in the storage capacitor between
the PFC and PWM sections

• Overvoltage, UVLO, and brownout protection

• PFC V

OVP with PFC Soft Start

CC

Block Diagram

4

3

5

6

VEAO

I

SENSE

–1V

V

DC

I

LIMIT

35µA

M1

M7

ONE PIN ERROR AMPLIFIER

PFC I

LIMIT

+

26k

40k

–

V

REF

M6

V

CC

7V

1.2V

PFC OFF

+

COMP

–

–1

M2

–4

PFC/PWM UVLO

OSCILLATOR

PWM – 134kHz

–

COMP

+

M3

R1 C1

PFC – 67kHz

PWM COMPARATOR

–

COMP

+

1.5V

General Description

The FAN4803 is a space-saving controller for power factor
corrected, switched mode power supplies that offers very
low start-up and operating currents.

Power Factor Correction (PFC) offers the use of smaller, lower
cost bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply fully compli­ant to IEC1000-3-2 specifications. The FAN4803 includes
circuits for the implementation of a leading edge, average
current “boost” type PFC and a trailing edge, PWM.

The FAN4803-1’s PFC and PWM operate at the same
frequency, 67kHz. The PFC frequency of the FAN4803-2 is
automatically set at half that of the 134kHz PWM. This
higher frequency allows the user to design with smaller
PWM components while maintaining the optimum operating
frequency for the PFC. An overvoltage comparator shuts
down the PFC section in the event of a sudden decrease in
load. The PFC section also includes peak current limiting for
enhanced system reliability.

7

V

30pF

DUTY CYCLE

LIMIT

DC I

–
+

CC

17.5V

M4

+
–

LIMIT

16.2V

COMP

+

COMP

–

VCC OVP

CONTROL

LOGIC

PFC

SOFT START

CONTROL

LOGIC

REF

PWM

V

REF

GND

PFC OUT

LEADING

EDGE PFC

TRAILING

EDGE PWM

PWM OUT

2

1

8

REV. 1.2.3 11/2/04

FAN4803 PRODUCT SPECIFICATION

Pin Configuration

FAN4803
8-Pin PDIP (P08)
8-Pin SOIC (S08)

PFC OUT

GND

I

SENSE

VEAO

1
2
3
4

TOP VIEW

8
7
6
5

PWM OUT
V

CC

I

LIMIT

V

DC

Pin Description

Pin Name Function

1 PFC OUT PFC driver output
2 GND Ground
3I

SENSE

Current sense input to the PFC current limit comparator
4 VEAO PFC one-pin error amplifier input
5V
6I
7V

DC

LIMIT

CC

PWM voltage feedback input

PWM current limit comparator input

Positive supply (may require an external shunt regulator)
8 PWM OUT PWM driver output

Absolute Maximum Ratings

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.

Parameter Min Max Unit

I

Current (average) 40 mA

CC

V

MAX 18.3 V

CC

I
Voltage on Any Other Pin GND – 0.3 V

Voltage -5 1 V

SENSE

CC

+ 0.3 V
Peak PFC OUT Current, Source or Sink 1 A
Peak PWM OUT Current, Source or Sink 1 A
PFC OUT, PWM OUT Energy Per Cycle 1.5 µJ
Junction Temperature 150 °C
Storage Temperature Range -65° 150 °C
Lead Temperature (Soldering, 10 sec) 260 °C
Thermal Resistance ( θ

JA

)
Plastic DIP 110 °C/W
Plastic SOIC 160 °C/W

Operating Conditions

Temperature Range

FAN4803CS-X 0°C to 70°C
FAN4803CP-X 0°C to 70°C

2

REV. 1.2.3 11/2/04

Ω

Ω

Ω

Ω

PRODUCT SPECIFICATION FAN4803

Electrical Characteristics

Unless otherwise specified, V

Symbol Parameter Conditions Min TYP MAX UNITS
One-pin Error Amplifier

V

Output Current T

EAO

Line Regulation 10V < V

V

OVP Comparator

CC

Threshold Voltage 15.5 16.3 16.8 V

PFC I

Comparator

LIMIT

Threshold Voltage -0.9 -1 -1.15 V
Delay to Output 150 300 ns

DC I

Comparator

LIMIT

Threshold Voltage 1.4 1.5 1.6 V
Delay to Output 150 300 ns

Oscillator

Initial Accuracy T
Voltage Stability 10V < V
Temperature Stability 2 %
Total Variation Over Line and Temp 60 67 74.5 kHz
Dead Time PFC Only 0.3 0.45 0.65 µs

PFC

Minimum Duty Cycle V
Maximum Duty Cycle V
Output Low Impedance 8 15
Output Low Voltage I

Output High Impedance 8 15
Output High Voltage I
Rise/Fall Time C

PWM

Duty Cycle Range FAN4803-2 0-41 0-47 0-50 %

Output Low Impedance 8 15
Output Low Voltage I

Output High Impedance 8 15
Output High Voltage I
Rise/Fall Time C

Supply

V

Clamp Voltage (V

CC

Start-up Current V
Operating Current V
Undervoltage Lockout Threshold 11.5 12 12.5 V
Undervoltage Lockout Hysteresis 2.4 2.9 3.4 V

Note:

1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.

= 15V, T

CC

= Operating Temperature Range (Note 1)

A

= 25°C, V

A

CC

= 25°C 60 67 74 kHz

A

CC

> 7.0V,I

EAO

< 4.0V,I

EAO

= –100mA 0.8 1.5 V

OUT

I

= –10mA, V

OUT

= 100mA, V

OUT

= 1000pF 50 ns

L

= 6V 34.0 36.5 39.0 µA

EAO

< 15V, V

EAO

< 15V 1 %

SENSE
SENSE

= 8V 0.7 1.5 V

CC

= 15V 13.5 14.2 V

CC

FAN4803-1 0-49.5 0-50 %

= –100mA 0.8 1.5 V

OUT

I

)I

CCZ

= –10mA, V

OUT

= 100mA, V

OUT

= 1000pF 50 ns

L

= 10mA 16.7 17.5 18.3 V

CC

= 11V, C

CC

= 15V, C

CC

= 8V 0.7 1.5 V

CC

= 15V 13.5 14.2 V

CC

= 0 0.2 0.4 mA

L

= 0 2.5 4 mA

L

= 6V 0.1 0.3 µA

= -0.2V 0 %
= 0V 90 95 %

REV. 1.2.3 11/2/04

3

FAN4803 PRODUCT SPECIFICATION

Functional Description

The FAN4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a syn­chronized Pulse Width Modulation (PWM) controller. It is
distinguished from earlier combo controllers by its low pin
count, innovative input current shaping technique, and very
low start-up and operating currents. The PWM section is
dedicated to peak current mode operation. It uses conven­tional trailing-edge modulation, while the PFC uses leading­edge modulation. This patented Leading Edge/Trailing Edge
(LETE) modulation technique helps to minimize ripple cur­rent in the PFC DC buss capacitor.

The FAN4803 is offered in two versions. The FAN4803-1
operates both PFC and PWM sections at 67kHz, while the
FAN4803-2 operates the PWM section at twice the fre­quency (134kHz) of the PFC. This allows the use of smaller
PWM magnetics and output filter components, while mini­mizing switching losses in the PFC stage.

In addition to power factor correction, sev eral protection fea­tures have been built into the FAN4803. These include soft
start, redundant PFC over-voltage protection, peak current
limiting, duty cycle limit, and under voltage lockout
(UVLO). See Figure 12 for a typical application.

Detailed Pin Descriptions

V

EAO

This pin provides the feedback path which forces the PFC
output to regulate at the programmed value. It connects to
programming resistors tied to the PFC output voltage and is
shunted by the feedback compensation network.

I

SENSE

This pin ties to a resistor or current sense transformer which
senses the PFC input current. This signal should be negative
with respect to the IC ground. It internally feeds the pulse­by-pulse current limit comparator and the current sense feed­back signal. The I
back is internally multiplied by a gain of four and compared
against the internal programmed ramp to set the PFC duty
cycle. The intersection of the boost inductor current
downslope with the internal programming ramp determines
the boost off-time.

trip level is –1V. The I

LIMIT

SENSE

feed-

control of the PWM stage. The current ramp is offset inter­nally by 1.2V and then compared against the opto feedback
voltage to set the PWM duty cycle.

PFC OUT and PWM OUT

PFC OUT and PWM OUT are the high-current power driv­ers capable of directly driving the gate of a power MOSFET
with peak currents up to ±1A. Both outputs are actively held
low when V

V

CC

V

is the power input connection to the IC. The V

CC

up current is 150µA . The no-load I
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the operating
frequency and the MOSFET gate charge (Qg), average
PFC and PWM output currents can be calculated as I
Qg x F. The average magnetizing current required for any
gate drive transformers must also be included. The V
is also assumed to be proportional to the PFC output voltage.
Internally it is tied to the V
providing redundant high-speed over-voltage protection
(OVP) of the PFC stage. V
UVLO circuitry, enabling the IC at 12V and disabling it at

9.1V. V
bypass capacitor placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
FAN4803.

V

is typically produced by an additional winding off the

CC

boost inductor or PFC Choke, providing a voltage that is pro­portional to the PFC output voltage. Since the V
voltage is 16.2V, an internal shunt limits V
an acceptable value. An external clamp, such as shown in
Figure 1, is desirable but not necessary.

is below the UVLO threshold level.

CC

current is 2mA. V

CC

OVP comparator (16.2V)

CC

also ties internally to the

CC

must be bypassed with a high quality ceramic

CC

CC

overvoltage to

CC

V

CC

1N4148

1N4148

1N5246B

start-

CC

CC

=

OUT

pin

CC

OVP max

V

DC

This pin is typically tied to the feedback opto-collector. It is
tied to the internal 5V reference through a 26k Ω resistor and
to GND through a 40k Ω resistor.

I

LIMIT

This pin is tied to the primary side PWM current sense resis­tor or transformer. It provides the internal pulse-by-pulse
current limit for the PWM stage (which occurs at 1.5V) and
the peak current mode feedback path for the current mode

4

GND

Figure 1. Optional V

V

is internally clamped to 16.7V minimum, 18.3V maxi-

CC

mum. This limits the maximum V
the IC while allowing a V
V

OVP. The max current through this zener is 10mA.

CC

which is high enough to trip the

CC

Clamp

CC

that can be applied to

CC

External series resistance is required in order to limit the
current through this Zener in the case where the V

voltage

CC

exceeds the zener clamp level.

REV. 1.2.3 11/2/04