Fairchild DM7490A service manual
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DM7490A
Decade and Binary Counters
DM7490A Decade and Binary Counters
August 1986
Revised March 2000
General Description
The DM7490A monolithic counter contains four masterslave flip-flops and additio nal ga ting to pr ovi d e a divid e-b ytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-five.
The counter has a gated zero reset and also has gated setto-nine inputs for use in BCD nine’s complement applications.
To use the maximum count length (decade or four-bit
binary), the B input is connected to the Q
input count pulses are applied to input A and the outputs
are as described in the app rop ria te F un c tion Table. A symmetrical divide-by-ten count can be obtained from the
counters by connecting the Q
applying the input count to the B input which gives a divideby-ten square wave at output Q
output to the A input and
D
.
A
output. The
A
Features
■ Typical power dissipation
145 mW
■ Count frequency 42 MHz
Ordering Code:
Order Number Package Number Package Description
DM7490AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006533 www.fairchildsemi.com
Function Tables
BCD Count Sequence (Note 1)
Count Outputs
DM7490A
0 LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5LHLH
6LHHL
7LHHH
8 HLLL
9HLLH
Count Outputs
0 LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5 HLLL
6HLLH
7HLHL
8HLHH
9HHLL
Q
D
BCD Bi-Quinary (5-2) (Note 2)
Q
A
Logic Diagram
Q
C
Q
D
Q
Q
Q
B
C
A
Q
B
Reset/Count Function Table
Reset Inputs Outputs
R0(1) R0(2) R9(1) R9(2) Q
DQCQBQA
H H L X LLLL
H H X L LLLL
XXHHHLLH
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT
H = HIGH Level
L = LOW Level
X = Don’t Care
Note 1: Output QA is connected to input B for BCD count.
Note 2: Output QD is c onnected to input A for bi- quinary count
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The J and K inputs sho wn without connec tion are for refere nce only and
are functionally at a H IG H lev el.
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