An IGT’s few input requirements and low On-state resistance
simplify drive circuitry and increase power efficiency in motorcontrol applications. The voltage-controlled, MOSFET-like
input and transfer characteristics of the insulated-gate transistor (IGT) (see EDN, September 29, 1983, pg 153 for IGT
details) simplify power-control circuitry when compared with
bipolar devices. Moreover, the IGT has an input capacitance
mirroring that of a MOSFET that has only one-third the powerhandling capability. These attributes allow you to design simple, low-power gate-drive circuits using isolated or level-shifting techniques. What’s more, the drive circuit can control the
IGT’s switching times to suppress EMI, reduce oscillation and
noise, and eliminate the need for snubber networks.
Use Optoisolation T o Avoid Ground Loops
The gate-drive techniques described in the following sections
illustrate the economy and flexibility the IGT brings to power
control: economy, because you can drive the device’s gate
directly from a preceding collector, via a resistor network, for
example; flexibil ity, because you can choose the drive circuit’s
impedance to yield a desired turn-off time, or you can use a
switchable im pedance that causes the IGT to act as a chargecontrolled device requiring less than 10 nanocoulombs of
drive charge for full turn-on.
Take Some Driving Lessons
Note the IGT’s straightforward drive compatibility with CMOS,
NMOS and open-collector TTL/HTL logic circuits in the
common-emitter configuration Figure 1A. R
off time, and the sum of R
and the parallel combination of R
3
and R2 sets the turn-on time. Drive-circuit requirements,
however, are more complex in the common-collector
configuration Figure 1B.
In this floating-gate-supply floating-control drive scheme, R
controls the gate supply’s power loss, R2 governs the turn-off
time, and the sum of R
and R2 sets the turn-on time. Figure
1
1C shows another common-collector configuration employing
a bootstrapped gate supply. In this configuration, R3 defines
the turn-off time, while the sum of R
2
on time. Note that the gate’s very low leakage allows the use
of low-consumption bootstrap supplies using very low-value
capacitors. Figure 1 shows two of an IGT’s strong points. In
the common-emitter Figure 1A, TTL or MOS-logic circuits can
drive the device directly. In the common-collector mode, you’ll
need lev el s hifting, using either a second power suppl y Figure
1B or a bootstrapping scheme Figure 1C.
through the logic circuit’s ground can create problems.
Optoisolation can solve this problem (Figure 2A.) Because of
the high common-mode dV/dt possible in this configuration,
you should use an optoisolator with ver y low isolation capacitance; the H11AV specs 0.5pF maximum.
In the common-collector circuits, power-switch current flowing
Application Note 7511
For optically isolated “relay-action” switching, it makes sense
to replace the phototransistor optocoupler with an H11L1
Schmitt-trigger optocoupler (Figure 2B).) For applications
requiring extremely high isolation, you can use an optical f iber
to provide the signal to the gate-control photodetector. These
circuit examples use a gate-discharge resistor to control the
IGT’s turn-off time. To exploit fully the IGT’s safe operating
area (SOA), this resistor allows time for the device’s minority
carriers to recombine. Furthermore, the recombination occurs
without any current crowding that could cause hot-spot formation or latch-up pnpn action. For very fast turn-off, you can use
a minimal snubber network, which allows the saf e use of lower
value gate resistors and higher collector currents.
V
CC
R
1
R
C
CONTROL
INPUT
OFF
ON
FIGURE 2A. AVOID GROUND-LOOP PROBLEMS BY USING AN
OPTOISOLATOR. THE ISOLATOR IGNORES SYSTEM GROUND CURRENTS AND ALSO PROVIDES HIGH COMMON-MODE RANGE.
2
H11AV2
R
3
LOAD
directly from TTL levels, thanks to its 1.2V, 20mA input
parameters.
Available photovoltaic couplers have an output-current
capability of approximately 100µA. Combined with
approximately 100kΩ equivalent shunt impedance and the
IGT’s input capacitance, this current level yields very long
switching times. These transition times (typically ranging to 1
msec) vary with the photovoltaic coupler’s drive current and the
IGT’s Miller-effect equivalent capacitance.
Figure 3 illustrates a typical photovoltaic-coupler drive along
with its transient response. In some applications, the
photovoltaic element can charge a storage capacitor that’s
subsequently switched with a phototransistor isolator. This
isolator technique - similar to that used in bootstrap circuits
pro v id e s rapid tu rn- o n and tu rn - o f f w hi l e maintai n in g s m a l l s i ze,
good isolation and low cost.
In common-collector applications involving high-voltage, reactive-load switching, capacitive currents in the low-level logic circuits can flow through the isolation capacitance of the control
element (eg, a pulse transformer, optoisolator, piezoelectric
coupler or level-shift transistor). These currents can cause
undesirable effects in the logic circuitry, especially in highimpedance, low-signal-level CMOS circuits.
+
I
ON
OFF
CONTROL
INPUT
DIG22
IGT
-
VCC = 300V
43k
1N5061
CONTROL
INPUT
OFF
ON
FIGURE 2B. A SCHMITT-TRIGGER OPTOIS OLATOR YIELDS
10µF
35V
H11L1
“SNAP-ACTION” TRIGGERING SIMILAR TO
THAT OF A RELAY.
5.6k5.6k
5.6k
LOAD
Pulse-Transformer Drive Is Cheap And Efficient
Photovoltaic couplers provide yet another means of driving the
IGT. Typically, these devices contain an array of small silicon
photovoltaic cells, illuminated by an infrared diode through a
transparent dielectric. The photovoltaic coupler provides an
isolated, controlled, remote dc supply without the need for
oscillators, rectifiers or filters. What’s more, you can drive it
OUTPUT
CURRENT
INPUT
CURRENT
FIGURE 3. AS ANOTHER OPTICAL-DRIVE OPTION, A PHOTO-
VOLTAIC COUPLER PROVIDES AN ISOLATED,
REMOTE DC SU PPIY TO THE IGT’S INPUT. ITS
LOW 100µA OUTPUT, HOWEVER, YIELDS LONG
IGT TURN-ON AND TURN-OFF TIMES.
012ms
The solution? Use fiber-optic components Figure 4 to eliminate the problems completely. As an added feature, this lowcost technique provides physical separation between the
power and logic circuitry, thereby eliminating the effects of
radiated EMI and high-flux magnetic fields typically found
near power-switching circuits. You could use this method
with a bootstrap-supply circuit, although the fiber-optic system’s reduced transmission efficiency could require a
gain/speed trade-off. The added bipolar signal transistor
minimizes the pot enti al for compromise.
A piezoelectric coup ler operationally similar to a pulse-train
drive transformer, but potentially less costly in high volume is
a small, ef ficient device with iso lation capability ranging to
4kV. What’s more, unlike optocouplers, they require no
auxiliary power supply. The piezo element is a ceramic
component in which electrical energy is converted to
mechanical energy, transmitted as an acoustic wave, and
then reconver ted to electrical energy at the output terminals
Figure 5A.
The piezo element’s maximum coupling efficiency occurs at
its resonant frequency, so the control oscillator must operate
at that freq uen cy. For example, the PZT61343 piezo c oup ler
in Figure 5B’s driver circuit requires a 108kHz, ±1%-accurate
astable multivibrator to maximize mechanical oscillations in
the ceramic material. This piezo element has a 1W max
power handling capability and a 30mA p-p max secondar y
current rating. The 555 timer shown provides compatible
waveforms while the R C ne twork sets the frequency.
Isolate With Galvanic Impunity
Do you require tried and true isolation? Then use
transformers; the IGT’s low gate requirements simplify the
design of independent, transformer-coupled gate-drive
supplies. The supplies can directly drive the gate and its
discharge resistor Figure 6, or they can simply replace the
level-shifting supplies of Figure 2. It’s good practice to use
pulse transformers in drive circuitry, both for IGT’s and
MOSFETs, because these components are economical,
rugged and hi ghly reliable.
+
ON
OFF
TRANSFORMER
CONTROL
INPUT
PULSE
1N914
1N914
2N5232
1k
IGT
C
1
-
FIGURE 6A. PROVIDING HIGH ISOLA TION A T LO W COST , PUL SE
TRANSFORMERS ARE IDEAL FOR DRIVING THE
IGT. AT SUFFICIENTLY HIGH FREQUENCIES, C
CAN BE THE IGT’S GATE-EMITTER CAPA CITANCE
ALONE.
+
ON OFF
CONTROL
INPUT
1N914
IGT
CR
-
1N914 RC = 3µSEC
FIGURE 6B. A HIGH-FREQUEN CY OSCI LL ATOR IN THE TRANS -
FORMER’S PRIMARY YIELDS UNLIMITED ONTIME CAP ABILITY.
In the pulse-on, pulse-off method Figure 6A, C1 stores a
positive pulse, holding the IGT on. At moderate frequencies
(several hundred Hertz and above), the gate-emitter
capacitance alone can store enough energy to keep the IGT
on; lower frequencies require an additional external capacitor.
Use of the common-base n-p-n bipolar transistor to discharge
the capacitance minimizes circuit loading on the capacitor.
This action extends continuous on-time capability without
capacitor refreshing; it also controls the gate-discharge time
via the 1kΩ emitter resistor.
1
VARIABLE
220V AC
3φ 60Hz
THREE-PHASE
BRIDGE
RECTIFIER
LOW VOLTAGE
TRANSFORMER
RECTIFIER
FILTER
SIGNAL PATH ISOLATOR
I
EG: OPTOCOUPLIER PIEZO COUPLER
24V DC
SWITCHING
REGULATOR
POWER SUPPLY
FOR CONTROL
CIRCUITS
VOLTAGE
ENABLE
ADJUST VOLTAGE
5V
VOLTAGE
CONTROLLED
OSCILATOR
24V
III
MOTOR
CONTROL
LOGIC
DC VOLTAGE
TIMING
AND DRIVE
I
SHUT DOWN
DRIVE
OSCILLATOR
THREE-PHASE
INVERTER
ENABLE
LOWER
LEGS
OVERLOAD
PROTECTION
IGT
3φ
INDUCTION
MOTOR
CURRENT
SENSE
SIGNAL
TACHOMETER
FEEDBACK
FIGURE 8. THIS 6-STEP 3-PHASE-MOTOR DRIVE USES THE IGT-DRIVE T ECHNIQUES DESCRIBED IN THE TEXT. THE REGULATOR AD-
JUSTS THE OUTPUT DEVICES’ INPUT LEVELS; THE VOLTAGE-CONTROLLED OSCILLATOR VARIES THE SWITCHING
FREQUENCY AND ALSO PROVIDES THE CLOCK FOR THE 3-PHASE TIMING LOGIC. THE V/F RATIO STAYS CONSTANT
TO MAINTAIN CONSTANT TORQUE REGARDLESS OF SPEED.
Using a high-frequency oscillator fo r pulse-train drive Figure
6B yields unlimited on-time capability. However, the scheme
requires an oscillator that can be tur ned on and off by the
control logic. A diode or zener clamp across the transformer’s primary will limit leakage -inductance flyback effects .
To optimize transformer efficiency, make the pulses’ voltage
x time products equal for both the On and the Off pulses. In
situations where the line voltage generates the drive power,
a simple relax ati on os cil lat or u sing a progra mm able uni junc tion transistor can der ive its power directly from the line to
provide a pulse train to the IGT gate.
The circuit shown in Figure 7 accommodates applications
involving lower frequencies (a few hundred Hertz and
below). The high oscillator frequency (greater than 20kHz)
helps keep the pulse transformer reasonably small. The volt-
7
L
1
D
1
C
325V
10A
1
R
R
Q
RR
1
D
2
Q
2
age-doubler circu itry impro ves the turn-on time and also provides long on-time capability. Although this design uses only
a 5V supply on the primary side of a standard trigger transformer, it provides 15V gate-to-emitter voltage.
1N914
OSCILLATOR
1:2
1N914
FIGURE 7. THIS DRIVING METHOD FOR LOW-FREQUENCY
SWITCHING PROVIDES 15V TO THE IGT’S GATE
D
3
Q
3
D
4
Q
RR
4
D
5
Q
5
NOTES:
D
6
Q
- Q6 = D94FR4
1
- D7 = 1N3913
D
1
- D13 = 1N914
D
Q
6
8
R = 4.7k,
C
L
1
= 100µF, 400V
1
= 40µH
1
/2W
0.001
µF
4.7k
0.001µF
INDUCTION
MOTOR
220V
IGT
FIGURE 9A. THE POWER INVERTER’S DRIVE CIRCUIT USES SIX IGTS TO DRIVE A 2-HP MOTOR.
o
180
Q1 ON
ON
Q
6
15o DELAY
Q2ON
ON
Q
3
o×
t
Q
ON
4
Q
ON
5
t
t
t
t
t0
OF EVERY 360o CYCLE;
φA
0
φB
0
φC
0
I
LA
0
I
LB
0
I
LC
FIGURE 9B. THE TIMING DIAGRAM SHOWS THAT EACH IGT
CONDUCTS FOR 165
THE DELAY IS NECESSARY TO AVOID CROSS
CONDUCTION.
V
AB
0t
V
BC
0
V
CA
0
I
LA
0
I
LB
0
I
LC
0
FIGURE 9C. THE THREE WINDINGS’ VOLTAGES AND CUR-
RENTS ARE SHOWN. NOTE THAT ALTHOUGH
COSTLY SNUBBER NETWORKS ARE ELIMINATED, FREEWHEELING DIODES ARE NEEDED; THE
IGTS HAVE NO INTRINSIC OUTPUT DIODE.
Polyphase motors, controlled by solid-state, adjustable-frequency ac drives, are used extensively in pumps, conveyors,
mills, machine tools and robotics applications. The specific control method could be either 6-st ep or pulse-width modulation.
This section describes a 6-step drive that uses some of the previously discussed drive techniques (see page 11 , “Latch-Up:
Hints, Kinks and Caveats”).
Figure 8 defines the drive’s block diagram. A 3-phase rectifier
converts the 220V ac to dc; the switching regulator varies the
output voltage to the IGT inverter. At the regulator’s output, a
large filter capacitor provides a stiff voltage supply to the
inverter.
The motor used in this example has a low slip characteristic
and is therefore very efficient. You can change the motor’s
speed by varying the inverter’s frequency. As the frequency
increases, however, the motor’s air-gap flux diminishes, reducing developed-torque capability. You can maintain the flux at a
constant level (as in a dc shunt motor) if you also vary the voltage so the V/F ratio remains constant.
Fiber-Optic Drive Eliminates Interference
In the example given, the switching regulator varies the IGT
inverter’s output by controlling its dc input; the voltage-controlled oscillator (VCO) adjusts the inverter’s switching frequency, thereby varying the output frequency. The VCO also
drives the 3-phase logic that provides properly timed pulsed
outputs to the piezo couplers that directly drive the IGT.
Sensing the dc current in the negative rail and inhibiting the
gate signa l protect the IGT from overload and shoot-through
(simultaneous conduction) conditions. If a fault continues to
exist for an appreciable period, inhibiting the switching regulator causes the inv erter to shut off. The inverter’s pow er-ou tput circuit is shown in Figure 9A; the corresponding timing
diagrams show resistive-load current waveforms that indicate the 3-phase power Figure 9B and waveforms of the output line voltage and cu rrent Figure 9C.
In Figure 9’s circuit, it appears that IGTs Q
conduct for 180
o
. Howe v er, in a practical situation, it’ s ne ces-
sary to provid e some t ime de lay (typic ally 1 0
through Q6 will
1
o
to 15o×) during the positive-to-negative transition periods in the phase
current. This delay allows the complementary IGTs to turn
off before their opposite members turn on, thus preventing
cross conduction and e ventual destruction of the IGTs.
Because of the time delay, the maximum conduction time is
o
of every 360o period. B ecaus e the IG Ts do n’t have an
165
integral diode, it’s necessary to connect an antiparallel diode
externally to allow the freewheeling current to flow. Inductor
limits the di/dt during fault conditions; freewheeling diode
L
1
D
clamps the IGT’s collector supply to the dc bus .
7
The peak full-load line current specified by the motor manufacturer determines the maximum steady-state current that
each transistor must switch. You must convert this RMSspecified current to peak values to specify the proper IGT. If
the input voltage regulator had a fixed output voltage and a
constant frequency, each IGT would be required to supply
the starting locked-rotor current to the motor. This current
could be as much as 15 times the full-load running current.
7
L
1
D
11
C
1
+
0 TO 325V
10A
FIGURE 10A. COMPONENT SELECTION IS IMPORTANT. THE IGT SELECTED CIRCUIT HANDLES 10A, 500V AT 150oC. THE ANTI-
PARALLEL DIODES HAVE A SIMILAR CURRENT RATING.
R
D
8
R
10
0.1
1
Q
Q
100
D
12
1
D
1
R
D
9
D
2
2
R
t
D(OFF)
t
Q
Q
t
F1
t
D(OFF)
F2
1k10k
R
GE
3
4
I
C
0.9I
D
13
D
3
R
D
10
D
4
R
t
F1
0.1I
C
0
t
F2
Q
5
D
5
Q
D
6
6
SWITCHES ON” (1, 4, 5),
(1, 3, 6), (2, 3, 6),
(2, 3, 5), (2, 4, 5)
C
TO
LOAD
FIGURE 10B. SELECT R TO YIELD THE DESIRED TURN-OFF TIME. FINALLY, L1’S VALUE DETERMINES THE FAULT-CONDITION
It’s impr ac tic al, however, to ra te an inverter based on lockedrotor current. You can avoid this necessity by adjusting the
switching regulator’s output voltage and by providing a fixed
output-current limit slightly higher than the maximum fullload current. This way, the current requirements during startup will never exceed the current capability of an efficiently
sized inverter.
For example, consider a 2-hp, 3-phase induction motor specifying VL at 230V RMS and full-load current (I
2.7k
1000pF
3.3k
VCO &
TIMING
LOGIC
2.5k
4
7
21
NE555
5V
8
3
56
A4.7k
1N914
0.001µF
5V
470
B
Q
2N3903
) at 6.2A
LFL
1k
1N914
4.7k
7
470
RMS. For the peak current of 8.766A, you can select IGT
type D94FR4. This device has a reverse-breakdown SOA
(RBSOA) of 10A, 500V for a clamped inductive load at a
junction temper ature o f 1 50
o
C. A 400V IGT coul d als o do the
job, but the 500V choice gives an additional derating safety
margin. You must set the current limit at 9A to limit the inrush current during start-up. Note that thanks to the IGT’s
adequate RBSOA, you don’t need turn-off snubbers.
24V
3
22µF
C
1
Q
2N3903
1N914
PIEZOCOUPLER
PZT61343
8
3
10
10
1N914
2N3903
Q
5
1N914
1N914
E
F
Q
4.7k
Q
4.7k
C
Q
D29E10
1k
8
2N3903
24V
470
D
470
D33030
Q
Q
4
DC BUS
1
D94FR4
φA
2
D94FR4
FIGURE 11A. PROVIDING PROPERLY TIMED DRIVE TO THE IGTS, THE CIRCUIT USES PIEZO COUPLING TO THE UPPER POWER
DEVICE. THE 3-TRANSISTOR DELAY CIRCUIT PROVIDES THE NEEDED 15
o
LAG TO THE LOWER IGT TO AVOID
CROSS CONDUCTION.
VOLTS
24V
F
24V
E
D
C
B
A
24V
5V
100kHz
5V
5V
TIME
TIME
TIME
TIME
TIME
FIGURE 11B. THE TIMING DIAGRAM SHOWS THE 555’S 108-KHz DRIVE TO THE PIEZO DEVICE AND THE LATTER’S SLOW
Figure 10A shows the inverter circuit configured for this
example. Diodes D
as the IGTs; consequently, they’re rated to handle peak currents of at least 8.766A. However, they only conduct for a
short time (15
requirement is relati vely small.
External circuitry can control the IGT’s current fall time.
Resistor R co ntr o ls t
, an inherent characteristic of the selected IGT. In this
t
F2
example, a 4.7-kΩ gate-to-emitter resistor provides the
appropri ate fall time. Th e choice of cu rrent-limiti ng inductor
is based on the IGT’s overload-current rating and the
L
1
action time (the sum of the sensor’s sensing and response
time and the IGT’s turn-off time) in fault conditions.
through D6 carry the same peak curr ent
1
o
to 20o of 180o), so their average-current
Figure 10B; there's no way to control
F1
You could use a set of flip flops and a multivibrator to generate the necessary drive pul se s and the corresponding 120o×
delay between the three phases in Figure 10’s circuit. A voltage-controlled oscillator serves to change the inverter’s output frequency. In this circuit, IGTs Q
isolated gate drive; the drive for Q
, Q3 and Q5 require
1
, Q4 and Q6 can be
2
referred to common. If you use optocouplers for isolation,
you’ll need three isolated or bootstrap power supplies (in
addition to the 5V and 24V po w er suppli es) t o drive th e IGTs .
Another alternative is to use transformer coupling.
o
Conduction Prevents Shoot-Through
165
Consider, however, using Figure 11A’s novel, low-cost circuit. It uses a piezo coupler to drive the isolated IGT. As
noted, the coupler needs a high-frequency square wave to
induce mec hanical oscill ations in its primary side. The 555
oscillator provides th e necessary 108-kHz waveform; its output is gated ac cording to the required timi ng logic and th en
applied to the pie z o c oupler’s primary. The coupler’s rectified
output drives the IGT’s gate; the 4.7kW gate-to-emitter resistor provides a discharge path for C
during the IGT’s turn-
GE
off. The circuit’s logic-timing diagram is shown in Figure 11B.
The piezo coupler’s slow response time Figure 12A contrib-
utes appro ximately 2
o
to the 15o to 20o turn-on/turn-off delay
needed to avoid shoot-through in the complementary pairs.
The corresp ondin g coll ector c urre nt is s hown in F igure 1 2B.
and its associated circuitry provide the remaining delay
C
1
as follows:
FIGURE 12A. THE PIEZO COUPLER’S SLOW RESPONSE IS NOT
FIGURE 12B. THE DRIVEN IGT 'S COLLEC T OR CURRENT IS
A DISADVANTAGE IN THIS ARTICLE’S CIRCUIT. IN
F ACT, IT CONTRIBUTES 2
TURN-ON/TURN-OF F DEL AY.
TRACEVERTICALHORIZONTAL
A5V/DIV200µSEC/DIV
B5V/DIV200µSEC/DIV
SHOWN
TRACEVERTICALHORIZONTAL
A3A/DIV200µSEC/DIV
B5V/DIV200µSEC/DIV
o
TO THE REQUIRED 15
When Q3’s base s wings negative, C1 - at this time discharged turns on Q
pulse to turn the IGT on. When Q
. Once C1 is charged, Q5 turns off, allowing a drive
5
’s base goes to ground, Q
7
turns on and discharges C1, initiating the IGT’s turn-off. Figure
13 shows the motor current and corresponding line voltage
under light-load Figure 12A and full-load Figure 12B conditions.
To complete the design of the 6-step motor drive, it’s necessary to consider protection circuitry for the output IGTs. The drive receives its
power from a switching supply already containing provisions for protection from line over-voltage and under-voltage and transient effects.
However, you still have to guard the power switches against unwanted effects on the output lines and the possibility of noise or other
extraneous signals causing gate-drive timing errors.
The best protection circuit must match the character istics of the power switch and the circuit’s bias conditions. The IGT is very rugged
during turn-on and conduction, but it requires time to dissipate minority carriers when turning off high currents and voltages. An analysis
of the possible malfunction condition
AC
LINE
INPUT
RECTIFIER
AND
FILTER
SWITCHING
POWER
SUPPLY
50 TO 320V DC
5V DC
HV
ADJUST
CONTROL
AND
TIMING
ISOLATIONISOLATION
24V DC
ISOLATION
ISOLATION
dI/dt LIMIT
UPPER 3
LOWER 3
IGT
SWITCHES
MOTOR
CHOPPER
RECYCLE
TIME
HV
DISABLE
GATE DRIVETURNOFF
COMPARATOR
AND LATCH
I LIMIT
10A
20A
AC
AV = 100
FIGURE 14. THE LOWEST COST SENSOR IMAGINABLE, A PIECE OF COPPER WIRE SERVES AS THE CURRENT MONITOR IN THIS SYS-
TEM. THE CHOPPED AND AMPLIFIED VOLTAGE DROP ACROSS THE WIRE TRIGGERS A GATE-DRIVE SHUT-OFF CIRCUIT
UNDER FAULT CONDITIONS.
The IGT is a rugged device, requiring no snubber network
when operating within its published safe-operating-area
(SOA) ratings. Within the SOA, the gate emitter voltage
controls the collector current. In fact, the IGT can conduct
three to four times the published maximum current if it’s in the
ON state and the junction temperature is +150
o
C maximum.
However, if the current exceeds the rated maximum, the IGT
could lose gate control and latch up during turn-off attempts.
The culprit is the parasitic SCR formed by the pnpn structure
shown in Figure 16. In the equivalent circuit, Q
MOSFET with a normal parasitic transistor (Q
emitter junction is shunted by the lo w-value resistance R
EMITTER METALPOLYSILICON GATE
P
N EPITAXIAL LAYER
MAIN CURRENT PATH
P+ SUBSTRATE
N+N+
MINORITY
CARRIER
INJECTION
is a power
1
) whose base-
2
P
.
1
Forward-Bias Latch-Up
Within the IGT’s current and junction-temperature ratings,
current does not flow through Q2 under forward-biased
conditions. When the current far exceeds its rated value, the
current flow through R
increases and Q3’s VCE also
1
increases because of MOSFET channel saturation. Once
Q3’s ICR1 drop exceeds Q2’s V
, Q2 turns on and
BE(ON)
more current flow bypasses the FET.
The positive feedback thus established causes the device to
latch in the forward-biased mode. The value of I
at which
C
the IGT latches on while in forward conduction is typically
three to four times the device’s maximum rated collector
current. When the collector current drops below the value
that provokes Q
turn-on , normal operation resu mes if chip
2
temperature is still within ratings.
If the gate-to-emitter resistance is too low, the Q
2-Q3
parasitic SCR can cause the IGT to latch up during turn-off.
During this period, R
power MOSFET Q
this increases Q
determines the drain-so urce d V/dt of
GE
. A low R1 causes a rapid rise in v ol tag e -
1
’s VCE, increasing both R1’s value and Q2’s
2
gain.
Because of st orage time, Q
’s collector current continues to
3
flow at a level that’s higher than normal for the FET bias.
During rapid turn-off, a portion of this current could flow in
’s base-emitter junction, causing Q2 to conduct. This
Q
2
process results in device latch-up; current distribution will
probably be less uniform than in the case of forward-bias
latch-up.
METAL COLLECTOR
COLLECTOR
Q
3
Q
GATE
FIGURE 16. THE IGT’S P ARASITIC SCR IS RESPONSIBLE FOR
THE DEVICE’S LATCH-UP CHARACTERISTICS.
2
Q
1
EMITTER
R
1
For large current overloads, the current flowing through R
can provoke SCR triggering. In the simplest terms, R1 represents the equivalent of a distributed resistor network, whose
magnitude is a function of Q2’s VCE. During normal IGT
operation, a positive gate voltage (greater than the threshold) applied betwee n Q1’s gat e and so urce turns the FET o n.
The FET then turns on Q
(a pnp transistor with very low
3
gain), causing a small portion of the total collector current to
flow through the R1 network.
To turn the IGT off, you must reduce the gate-to-emitter
voltage to zero. This turns Q1 off, thus initiating the turn-off
sequence within the device. Total fall time includes currentfall-time one (tF1) and current-fall-time two (tF2)
components. The turn-off is a function of the gate-emitter
resistance, Q3’s storage time and the value of VGE prior to
turn-off. Device characteristics fix both the delay time and
the fall time.
Because the gains of Q2 and Q3 increase with temperature
and V
, latching current - high at +25oC - decreases as a
CE
function of increasing junction temperature for a given gateto-emitter resistance.
How do you test an IGT’s turn-off latching characteristic?
Consider the circuit in Figure 17. Q
’s base-current pulse
1
width is set appro xim ately 2 µsec great er than the IGT’s gatevoltage pulse width. This way, the device under test (DUT)
can be switched through Q
when reverse-bias latch-up
1
occurs. This circuit allows you to test an IGT’s latching
current nondestructively.
The results? Clamped-inductive-load testing with and
1
without snubbers reveals that snubbering increases current
handling dramatically: With RGE = 1kΩ, a 0.02µF snubber
capacitor increases current capability from 6A to 10A; with
RGE = 5kΩ, a 0.09µF snubber practically doubles capacity
(25A vs 13A).
Conclusions? You can double the IGT’s latching current by
increasing RGE from 1kΩ to 5kΩ, and double it again with a
polarized snubber using CS < 0 .1µF. The IGT is therefore
useful in situations where the device must conduct currents
of five to six times normal levels for short periods.
Finally, you can also use the latch ing beh a vior to y o ur adv a ntage under fault conditions. In other words, if the device
latches up during turn-off under normal operation, you could
arrange it so that a suitable snubber is switched electronically across the IGT.
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Rev. H5
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