Fairchild 74ABT16373 service manual
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74ABT16373
16-Bit Transparent D-Type Latch with 3-STATE Outputs
74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
March 1994
Revised May 2005
General Description
The ABT16373 con tains sixteen non-inver ting latc hes with
3-STAT E outputs and is intended for bus oriented applications. The device is byte cont rolled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE
high Z state.
) is LOW. When OE is HIG H, the o utp uts are in
Features
■ Separate control logic for each byte
■ 16-bit version of the ABT373
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
■ Guaranteed latch-up protection
Ordering Code:
Order Number Package Number Package Description
74ABT16373CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16373CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab l e in Tape and Reel. Specify by appending suffix lette r “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names Description
OE
n
LE
n
D
0–D15
O
0–O15
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Output Enable Input (Active LOW)
Latch Enable Input
Data Inputs
Outputs
Functional Description
The ABT16373 contains sixteen D-type latches with
3-STATE standard outputs. The devi ce is byte controlled
with each byte funct ioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
74ABT16373
byte. When the Latch E nable (LE
enters the latches. In this condition the la tches are
the D
n
) input is HIGH, data on
n
transparent, i.e., a latch output will change states each time
its D input changes. When LE
is LOW, the latches store
n
information that was prese nt on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
STATE standard outputs are controlled by the Output
Enable (OE
puts are in the 2-state mode. When OE
) input. When OEn is LOW, the standard out-
n
is HIGH, the stan-
n
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Logic Diagrams
. The 3-
n
Truth Tables
Inputs Outputs
LE
OE
1
XH X Z
HL L L
HL H H
L L X (Previous)
Inputs Outputs
LE
OE
2
XH X Z
HL L L
HL H H
LL X (Previous)
H HIGH Voltage Level
L
LOW Voltage Level
Immaterial
X
High Impedance
Z
Previous
previous output prior to HIGH-to-LOW transition of LE
D0–D
1
2
D8–D
7
15
O0–O
O8–O
7
15
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