Fairchild 74ABT162244 service manual

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74ABT162244
16-Bit Buffer/Line Driver with

25: Series Resistors in the Outputs

74ABT162244 16-Bit Buffer/Line Driver with 25: Series Resistors in the Outputs

April 1992
Revised May 2005

General Description

The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a m emory
and address driver, clock driver, or bus oriented transmit­ter/receiver. The device is nibble controlled. Individual
3-STATE control inputs can be sho rted t oge the r for 8-bit or
16-bit operation.

The 25

:

series resistors in the outputs reduce ringing and

eliminate the need for external resistors.

Features

■ Separate control logic for each nibble

■ 16-bit version of the ABT2244

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

Ordering Code:

Order Number Package Number Package Description

74ABT162244CSSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74ABT162244CSSX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74ABT162244CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

74ABT162244MTDX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Logic Symbol

[RAIL]

[TAPE and REEL]

[RAIL]

[TAPE and REEL]

Connection Diagram

Pin Descriptions

Pin Names Description

OE

n

I

0–I15

O

0–O15

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Output Enable Input (Active LOW)
Inputs
Outputs

Truth Tables

Inputs Outputs

OE

1

74ABT162244

LL L
LH H
HX Z

Inputs Outputs

OE

3

LL L
LH H
HX Z

Inputs Outputs

OE

2

LL L
LH H
HX Z

I0–I

I8–I

I4–I

Logic Diagram

3

11

7

O0–O

O8–O

O4–O

3

11

7

Inputs Outputs

OE

4

I12–I

15

O12–O

15

LL L
LH H
HX Z

H HIGH Voltage Level
L

LOW Volt age Level

Immaterial

X

High Impedance

Z

Functional Description

The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble funct ioning ide ntically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.

Schematic of each Output

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Absolute Maximum Ratings(Note 1) Recommended Operating

Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias

Pin Potential to Ground Pin

V

CC

Input Voltage (Note 2)
Input Current (Note 2)

65q

C to 150qC

55q

C to 125qC

55q

C to 150qC



0.5V to 7.0V



0.5V to 7.0V



30 mA to 5.0 mA

Voltage Applied to Any Output

in the Disabled or



Power-Off State
in the HIGH State

0.5V to 5.5V



0.5V to V

Current Applied to Output

in LOW State (Max) twice the rated I

DC Latchup Source Current

OL



500 mA

Over Voltage Latchup (I/O) 10V

Conditions

Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (

Data Input 50 mV/ns
Enable Input 20 mV/ns

CC

Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation

(mA)

under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient t o protect inputs.

'V/'

t)

DC Electrical Characteristics

Symbol Parameter Min Typ Max Units

V
V
V
V

V
I

I
I

V

I
I

I
I
I
I
I

I

I

I

Input HIGH Voltage 2.0 V Recognized HIGH Signal

IH

Input LOW Voltage 0.8 V Recognized LOW Signal

IL

Input Clamp Diode Voltage

CD

Output HIGH Voltage 2.5 V Min IOH 3 mA

OH

Output LOW Voltage 0.8 V Min IOL 12 mA

OL

Input HIGH Current 1

IH

Input HIGH Current Breakdown Test 7

BVI

Input LOW Current

IL

Input Leakage T est 4 .75 V 0.0 IID 1.9 PA

ID

Output Leakage Current 10

OZH

Output Leakage Current

OZL

Output Short-Circuit Current

OS

Output High Leakage Current 50

CEX

Bus Drainage Test 100

ZZ

Power Supply Current 2.0 mA Max All Outputs HIGH

CCH

Power Supply Current 60 mA Max All Outputs LOW

CCL

Power Supply Current 2.0 mA Max OEn V

CCZ

Additional ICC/Input Outputs Enabled 3.0 mA VI VCC  2.1V

CCT

Dynamic I

CCD

Note 3: Guaranteed, but not tested.

CC

(Note 3) 0.1 MHz OEn GND

Outputs 3-STATE 3.0 mA Max Enable Input VI VCC  2.1V
Outputs 3-STATE 50

No Load mA/

2.0 V Min IOH 32 mA



100



1.2 V Min IIN 18 mA

1V



1



1V



10



275 mA Max V

V

CC

P

AMax

P

AMaxVIN 7.0V

P

AMax

P

A0  5.5V V

P

A0  5.5V V

P

AMaxV

P

A0.0V

P

A Data Input VI VCC  2.1V

VIN 2.7V (Note 3)

V

IN

VIN 0.5V (Note 3)

0.0V

IN

All Other Pins Grounded

2.7V; OEn 2.0V

OUT

0.5V; OEn 2.0V

OUT

0.0V

OUT

V

OUT

5.5V; All Others GND

OUT

All Others at VCC or GND

All Others at VCC or GND
Outputs OPEN

Max

One Bit Toggling, 50% Duty Cycle

Conditions

CC

CC

CC

40q

C to 85qC



4.5V to 5.5V

74ABT162244

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