Fairchild 74ABT126 service manual
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74ABT126
Quad Buffer with 3-STATE Outputs
74ABT126 Quad Buffer with 3-STATE Outputs
January 1995
Revised February 2005
General Description
The ABT126 contains four indepe ndent non-in verting buffers with 3-STATE outputs.
Features
■ Non-inverting buffers
■ Output sink capability of 64 mA, source capability of
32 m
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
■ Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT126CSC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ABT126CSJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT126CMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT126CMTCX_NL
(Note 1)
Devices also availab l e in Tape and Reel. Specify by appending suffix lette r “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free pac k age (per JEDEC J-S T D -020B). Device availa ble in Tape and Reel only.
Package
Number
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Package Descript ion
Connection Diagram Pin Descriptions
Pin Names Descriptions
, B
A
n
n
O
n
Inputs
Outputs
Function Table
Inputs Output
A
n
HLL
HHH
LXZ
H HIGH Voltage Level
LOW Voltage Level
L
HIGH Impedance
Z
X
Immaterial
© 2005 Fairchild Semiconductor Corporation DS011692 www.fairchildsemi.com
B
n
O
n
Absolute Maximum Ratings(Note 2) Recommended Operating
Storage Temperature
Ambient Temperature under Bias
74ABT126
Junction Temperature under Bias
Pin Potential to Ground Pin
V
CC
Input Voltage (Note 3)
Input Current (Note 3)
65q
C to 150qC
55q
C to 125qC
55q
C to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
0.5V to 5.5V
0.5V to V
Current Applied to Output
in LOW State (Max) twice the rated I
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup (I/O) 10V
OL
300 mA
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
Data Input 50 mV/ns
Enable Input 100 mV/ns
CC
(mA)
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
'V/'
DC Electrical Characteristics
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
IH
I
BVI
I
IL
V
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
I
CCD
Note 4: Guaranteed, but not tested.
Note 5: For 8 bits toggling, I
Input HIGH Voltage 2.0 V Recognized HIGH Signal
IH
Input LOW Voltage 0.8 V Recognized LOW Signal
IL
Input Clamp Diode Voltage
CD
Output HIGH Voltage 2.5 V Min IOH 3 mA
OH
Output LOW Voltage 0.55 V Min IOL 64 mA
OL
Input HIGH Current 1
Input HIGH Current Breakdown Test 7
Input LOW Current
Input Leakage Test 4.75 V 0.0 IID 1.9 PA, All Other Pin Grounded
ID
Output Leakage Current 10
Output Leakage Current
Output Short-Circuit Current -100
Output HIGH Leakage Current 50
Bus Drainage Test 100
Power Supply Current 50
Power Supply Current 15 mA Max All Outputs LOW
Power Supply Current 50
Additional ICC/Input Outputs Enabled 1.5 mA
Dynamic I
CC
(Note 4) 0.1 MHz OEn GND, (Note 5)
Outputs 3-STATE 1.5 mA Enable Input VI VCC 2.1V
Outputs 3-STATE 50
No Load mA/
0.8 mA/MHz.
CCD
2.0 V Min IOH 32 mA
1.2 V Min IIN 18 mA
1V
1
1V
10
275 mA Max V
V
CC
P
AMax
P
AMaxVIN 7.0V
P
AMax
P
A0 5.5V V
P
A0 5.5V V
P
AMaxV
P
A0.0V
P
A Max All Outputs HIGH
P
AMaxOEn VCC;
P
A Data Input VI VCC 2.1V
VIN 2.7V (Note 4)
IN
VIN 0.5V (Note 4)
IN
OUT
OUT
OUT
OUT
OUT
All Others at VCC or Ground
VI VCC 2.1V
Max
All Others at VCC or Ground
Outputs Open
Max
One Bit Toggling, 50% Duty Cycle
40q
C to 85qC
4.5V to 5.5V
t)
Conditions
V
CC
0.0V
2.7V; OEn 2.0V
0.5V; OEn 2.0V
0.0V
V
CC
5.5V; All Others GND
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