Fairchild 74ABT125 service manual
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74ABT125
Quad Buffer with 3-STATE Outputs
74ABT125 Quad Buffer with 3-STATE Outputs
March 1994
Revised February 2005
General Description
The ABT125 contains four indepe ndent non-in verting buffers with 3-STATE outputs.
Features
■ Non-inverting buffers
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
■ Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT125CSC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ABT125CSJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT125CMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT125CMTCX_NL
(Note 1)
Device also availab le in Tape and Reel. Specify by appending suffix lette r “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free pac k age (per JEDEC J-S T D -020B). Device availa ble in Tape and Reel only.
Package
Number
MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Package Description
Connection Diagram Pin Descriptions
Pin Names Descriptions
, B
A
n
n
O
n
Inputs
Outputs
Function Table
Inputs Output
A
H HIGH Voltage Level
L
LOW Voltage Level
HIGH Impedance
Z
Immaterial
X
© 2005 Fairchild Semiconductor Corporation DS011667 www.fairchildsemi.com
B
n
L L L
L H H
H X Z
n
O
n
Absolute Maximum Ratings(Note 2) Recommended Operating
Storage Temperature 65qC to 150qC
55q
Ambient Temperature under Bias
74ABT125
Junction Temperature under Bias
Pin Potential to
V
CC
Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
C to 125qC
55q
C to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
0.5V to 5.5V
0.5V to V
Current Applied to Output
in LOW State (Max) twice the rated I
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup (I/O) 10V
OL
300 mA
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
Data Input 50 mV/ns
Enable Input 20 mV/ns
CC
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
(mA)
under these conditi ons is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
'V/'
DC Electrical Characteristics
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
I
I
V
I
I
I
I
I
I
I
I
I
I
IH
BVI
IL
OZH
OZL
OS
CEX
ZZ
CCH
CCL
CCZ
CCT
CCD
Input HIGH Voltage V Recognized HIGH Signal
IH
Input LOW Voltage 0.8 V Recognized LOW Signal
IL
Input Clamp Diode Voltage
CD
Output HIGH Voltage 2.5 V Min IOH 3 mA
OH
Output LOW Voltage 0.55 V Min IOL 64 mA
OL
Input HIGH Current 1
Input HIGH Current Breakdown Test 7
Input LOW Current
Input Leakage Test V 0.0 IID 1.9 PA, All Other Pin Grounded
ID
Output Leakage Current 10
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current 50
Bus Drainage Test 100
Power Supply Current 50
Power Supply Current 15 mA Max All Outputs LOW
Power Supply Current 50
Additional I
Dynamic I
(Note 4) 0.1 MHz OEn GND, (Note 5)
Note 4: Guaranteed, but not tested.
Note 5: For 8 bits toggling, I
/Input OutputsEnabled 1.5 mA Max VI V
CC
CC
Outputs 3-STATE 1.5 mA Enable Input VI VCC 2.1V
Outputs 3-STATE 50
No Load mA/ Max Outputs Open
0.8 mA/MHz.
CCD
2.0 V Min IOH 32 mA
1.2 V Min IIN 18 mA
1V
1
1V
10
275 mA Max V
V
CC
P
AMax
P
AMaxVIN 7.0V
P
AMax
P
A05.5V V
P
A05.5V V
P
AMaxV
P
A0.0V
P
A Max All Outputs HIGH
P
AMaxOEn VCC;
P
A Data Input V I VCC 2.1V
VIN 2.7V (Note 4)
IN
VIN 0.5V (Note 4)
IN
OUT
OUT
OUT
OUT
OUT
All Others at V
All Others at VCC or Ground
One Bit Toggling, 50% Duty Cycle
40q
C to 85qC
4.5V to 5.5V
t)
Conditions
V
CC
0.0V
2.7V; OEn 2.0V
0.5V; OEn 2.0V
0.0V
V
CC
5.5V; All Others GND
or Ground
CC
2.1V
CC
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